Varun Wadekar 8f0e22d560 Tegra194: SiP function ID to read SMMU_PER registers ... This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER error records from all supported SMMU blocks. The register values are passed over to the client via CPU registers X1 - X3, where X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0] X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2] X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4] Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-03-21 19:00:05 -07:00
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drivers	Tegra194: Update t194_nvg.h to v6.7	2020-03-18 17:46:52 -07:00
plat_memctrl.c	Tegra: smmu: remove context save sequence	2020-03-11 13:37:26 -07:00
plat_psci_handlers.c	Tegra194: reset power state info for CPUs	2020-03-18 17:47:36 -07:00
plat_secondary.c	Tegra194: store TZDRAM base/size to scratch registers	2020-03-11 13:31:12 -07:00
plat_setup.c	Tegra194: enable dual execution for EL2 and EL3	2020-03-18 17:47:03 -07:00
plat_sip_calls.c	Tegra194: SiP function ID to read SMMU_PER registers	2020-03-21 19:00:05 -07:00
plat_smmu.c	Tegra: smmu: remove context save sequence	2020-03-11 13:37:26 -07:00
plat_trampoline.S	Tegra: smmu: remove context save sequence	2020-03-11 13:37:26 -07:00
platform_t194.mk	Tegra194: enable spe-console functionality	2020-01-28 09:43:10 +00:00