Bryan O'Donoghue 520f864e66 bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed ... A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to programming the lower-order 16 bits of the SPSR to populate into the CPSR on eret. The BL1 smc-handler code is identical and has the same shortfall in programming the SPSR from the platform defined struct entry_point_info->spsr. msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In order to ensure the 16 lower-order processor mode bits x->[15:8] and c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1. This change ensures we capture the x field, which we are interested in and not the f field which we are not. Fixes: f3b4914be3 ('AArch32: Add generic changes in BL1') Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>		2019-03-13 10:08:50 +00:00
..
bl1_arch_setup.c	bl1: include bl1_private.h in aarch* files	2017-06-23 09:38:06 +02:00
bl1_context_mgmt.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl1_entrypoint.S	BL1: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl1_exceptions.S	bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed	2019-03-13 10:08:50 +00:00