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Cortex-A78 erratum 2376745 is a cat B erratum that applies to revisions r0p0 - r1p2 and is still open. The workaround is to set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidation to other PE caches. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401784 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I6f1a3a7d613c5ed182a7028f912e0f6ae3aa7f98 |
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| .. | ||
| alt-boot-flows.rst | ||
| auth-framework.rst | ||
| cpu-specific-build-macros.rst | ||
| firmware-design.rst | ||
| index.rst | ||
| interrupt-framework-design.rst | ||
| psci-pd-tree.rst | ||
| reset-design.rst | ||
| trusted-board-boot-build.rst | ||
| trusted-board-boot.rst | ||