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Dimitris Papastamos f06890ea89 Refactor AMU support for Cortex A75 
This patch also fixes the assumption that the counters are disabled on
the resume path.  This is incorrect as the AMU counters are enabled
early in the CPU reset function before `cpuamu_context_restore()`
runs.

Change-Id: I38a94eb166a523f00de18e86860434ffccff2131
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
 		2018-02-27 13:28:41 +00:00
..
aem_generic.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
cortex_a35.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
cortex_a53.S CPU: Correct names of implementation-defined aux regs 2017-08-29 13:52:48 +01:00
cortex_a55.S Fix order of #includes 2017-07-12 14:45:31 +01:00
cortex_a57.S Print erratum application report for CVE-2017-5715 2018-01-18 10:36:10 +00:00
cortex_a72.S Print erratum application report for CVE-2017-5715 2018-01-18 10:36:10 +00:00
cortex_a73.S Print erratum application report for CVE-2017-5715 2018-01-18 10:36:10 +00:00
cortex_a75.S Refactor AMU support for Cortex A75 2018-02-27 13:28:41 +00:00
cortex_a75_pubsub.c Refactor AMU support for Cortex A75 2018-02-27 13:28:41 +00:00
cpu_helpers.S bl2-el3: Add BL2_EL3 image 2018-01-18 09:42:35 +00:00
cpuamu.c Refactor AMU support for Cortex A75 2018-02-27 13:28:41 +00:00
cpuamu_helpers.S Factor out CPU AMU helpers 2018-02-27 13:28:41 +00:00
denver.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
workaround_cve_2017_5715_bpiall.S Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75 2018-01-29 09:58:57 +00:00
workaround_cve_2017_5715_mmu.S Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75 2018-01-29 09:58:57 +00:00