f1be00da0b
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
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arm_gicv3_common.c | ||
gic500.c | ||
gic600.c | ||
gic600_multichip.c | ||
gic600_multichip_private.h | ||
gicv3_helpers.c | ||
gicv3_main.c | ||
gicv3_private.h |