Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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cci	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
ccn	Switch AARCH32/AARCH64 to __aarch64__	2019-08-01 13:45:03 -07:00
css	Unify type of "cpu_idx" across PSCI module.	2020-01-10 17:11:51 +00:00
fvp	fvp: pwrc: Move to drivers/ folder	2019-01-25 16:04:11 +00:00
gic	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
pl011	Correct UART PL011 initialization calculation	2019-10-08 13:58:25 +01:00
pl061	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
sbsa	libc: Consolidate unified definitions	2019-12-06 11:37:19 +01:00
scu	drivers: add a driver for snoop control unit	2020-01-03 10:44:28 +00:00
smmu	SMMUv3:Changed retry loop to delay timer(GENFW-3329)	2019-11-01 10:51:07 -06:00
sp804	Remove several warnings reported with W=2	2019-04-01 10:43:42 +01:00
sp805	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
tzc	tzc: remove deprecated types	2019-04-03 14:55:18 +01:00