Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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drivers	ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID	2019-04-23 11:09:13 -04:00
k3_bl31_setup.c	ti: k3: common: Allow USE_COHERENT_MEM for K3	2019-04-26 11:50:13 -04:00
k3_console.c	ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines	2019-04-19 12:56:24 -04:00
k3_gicv3.c	ti: k3: common: Add support for runtime detection of GICR base address	2019-01-22 13:11:09 -06:00
k3_helpers.S	ti: k3: common: Set L2 latency on A72 cores	2019-05-22 12:07:52 -05:00
k3_psci.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
k3_topology.c	ti: k3: common: Remove MSMC port definitions	2019-04-30 09:41:06 -04:00
plat_common.mk	ti: k3: common: Add PIE support	2019-10-29 14:27:11 +00:00