Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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allwinner	allwinner: Unify Platform specific defines for PSCI module	2020-01-24 13:14:34 +00:00
amlogic	Merge changes from topic "amlogic-g12a" into integration	2019-09-27 09:53:40 +00:00
arm	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
common	Merge "Unify type of "cpu_idx" across PSCI module." into integration	2020-01-10 19:39:17 +00:00
hisilicon	hisilicon: Unify Platform specific defines for PSCI module	2020-01-24 13:01:27 +00:00
imx	imx: Unify Platform specific defines for PSCI module	2020-01-24 13:14:08 +00:00
intel/soc	intel: Unify Platform specific defines for PSCI module	2020-01-24 13:15:11 +00:00
layerscape	layerscape: Unify Platform specific defines for PSCI module	2020-01-24 13:15:40 +00:00
marvell	marvell: Unify Platform specific defines for PSCI module	2020-01-24 13:14:55 +00:00
mediatek	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
nvidia/tegra	Tegra194: mce: remove unused NVG functions	2020-01-23 09:03:51 -08:00
qemu	qemu: Unify Platform specific defines for PSCI module	2020-01-24 13:15:33 +00:00
renesas/rcar	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
rockchip	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
rpi	Merge "rpi3/4: Add support for offlining CPUs" into integration	2020-01-20 22:16:43 +00:00
socionext	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
st	st: Unify Platform specific defines for PSCI module	2020-01-24 13:15:48 +00:00
ti/k3	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
xilinx	Merge "Xilinx zynqmp: add missing pin control group for ethernet 0." into integration	2020-01-24 10:02:07 +00:00