Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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aarch64	Prevent speculative execution past ERET	2020-01-22 21:42:51 +00:00
include	rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B	2019-08-29 13:02:30 +02:00
bl2_cpg_init.c	rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*	2019-08-16 15:15:12 +02:00
bl2_interrupt_error.c	rcar_gen3: plat: Dump EL3 interrupt error registers	2019-01-08 14:08:44 +01:00
bl2_plat_mem_params_desc.c	rcar_gen3: plat: Pass DT to OpTee OS	2020-01-06 03:07:35 +01:00
bl2_plat_setup.c	rcar_gen3: Add missing #{address,size}-cells into generated DT	2020-01-15 05:18:03 +01:00
bl2_secure_setting.c	rcar_gen3: plat: Add initial D3 support	2019-04-02 03:40:51 +02:00
bl31_plat_setup.c	rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*	2019-08-16 15:15:12 +02:00
plat_image_load.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
plat_pm.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
plat_storage.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
plat_topology.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
platform.mk	rcar_gen3: drivers: ddr: Move DDR drivers out of staging	2020-01-06 03:07:35 +01:00
rcar_common.c	Update renesas platform to not rely on undefined overflow behaviour	2019-07-11 12:10:58 +01:00