Siva Durga Prasad Paladugu d69bbd0e80 xilinx: versal: Wire silicon default setup ... Add new option for serial and default clock setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a		2020-01-15 11:04:05 -08:00
..
plat_ipi.h	xilinx: Add support to send PM API to PMC using IPI for versal	2020-01-15 11:01:37 -08:00
plat_macros.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
plat_pm_common.h	xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API	2020-01-15 11:02:43 -08:00
plat_private.h	xilinx: versal: Add PSCI APIs for suspend/resume	2020-01-15 11:03:16 -08:00
platform_def.h	versal: Increase OCM memory size for DEBUG builds	2020-01-15 11:04:00 -08:00
versal_def.h	xilinx: versal: Wire silicon default setup	2020-01-15 11:04:05 -08:00