Varun Wadekar e10842167b Tegra: init normal/crash console for platforms ... The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-02-22 09:16:34 -08:00
..
aarch64	Tegra: init normal/crash console for platforms	2017-02-22 09:16:34 -08:00
drivers	Tegra: Memory Controller Driver (v1)	2017-02-22 09:16:34 -08:00
tegra_bl31_setup.c	Tegra: init normal/crash console for platforms	2017-02-22 09:16:34 -08:00
tegra_common.mk	Tegra: Memory Controller Driver (v1)	2017-02-22 09:16:34 -08:00
tegra_delay_timer.c	Tegra: introduce delay timer support	2015-07-17 19:06:36 +05:30
tegra_gic.c	Add missing features to the Tegra GIC driver	2015-06-22 14:55:49 +05:30
tegra_pm.c	Tegra: add tzdram_base to plat_params_from_bl2 struct	2017-02-22 09:16:34 -08:00
tegra_topology.c	Tegra: remove support for legacy platform APIs	2015-12-04 15:41:20 -08:00