Joel Hutton f999faca06 Add note about erratum 814220 for A7 ... On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>		2019-04-10 10:57:58 +01:00
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arm32_aeabi_divmod.c	Correct typographical errors	2019-01-15 15:16:02 +00:00
arm32_aeabi_divmod_a32.S	ARMv7: division support for missing __aeabi_*divmod	2017-11-08 14:42:07 +01:00
armclang_printf.S	libc: armclang: Implement compiler printf symbols	2018-08-22 10:26:05 +01:00
cache_helpers.S	Add note about erratum 814220 for A7	2019-04-10 10:57:58 +01:00
misc_helpers.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00