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Add note about erratum 814220 for A7 

On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.

Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
This commit is contained in:
Joel Hutton 2019-04-09 14:45:34 +01:00 committed by Joel Hutton
parent a738e1554c
commit f999faca06
1 changed files with 3 additions and 1 deletions
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4
lib/aarch32/cache_helpers.S
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@ -124,7 +124,9 @@ loop3:
level_done:
add r1, r1, #2 // increment the cache number
cmp r3, r1
dsb sy // ensure completion of previous cache maintenance instruction
// Ensure completion of previous cache maintenance instruction. Note
// this also mitigates erratum 814220 on Cortex-A7
dsb sy
bhi loop1
mov r6, #0