johpow01 3a2710dcab Workaround for Cortex A78 erratum 1951500 ... Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3		2021-01-13 13:54:18 -06:00
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arch	Add support for FEAT_MTPMU for Armv8.6	2020-12-11 12:49:20 +00:00
bl1	Specify signed-ness of constants	2020-08-14 11:36:05 +00:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
bl32	spd: tlkd: support new TLK SMCs for RPMB service	2020-03-21 19:00:05 -07:00
common	Don't return error information from console_flush	2020-10-09 10:21:50 -05:00
drivers	cadence: Change logic in uart driver	2021-01-11 17:28:00 +00:00
dt-bindings	fdts: stm32mp1: realign device tree with kernel	2020-09-24 09:07:57 +02:00
export	Increase type widths to satisfy width requirements	2020-10-12 10:55:03 -05:00
lib	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
plat	plat: arm: Increase SP max size	2020-12-14 11:50:10 +00:00
services	SPMC: manifest changes to support multicore boot	2020-08-20 18:06:06 +01:00
tools_share	lib: fconf: Implement a parser to populate CoT	2020-09-15 16:13:26 +01:00