Soby Mathew 63b8440fcc TSP: Allow preemption of synchronous S-EL1 interrupt handling ... Earlier the TSP only ever expected to be preempted during Standard SMC processing. If a S-EL1 interrupt triggered while in the normal world, it will routed to S-EL1 `synchronously` for handling. The `synchronous` S-EL1 interrupt handler `tsp_sel1_intr_entry` used to panic if this S-EL1 interrupt was preempted by another higher priority pending interrupt which should be handled in EL3 e.g. Group0 interrupt in GICv3. With this patch, the `tsp_sel1_intr_entry` now expects `TSP_PREEMPTED` as the return code from the `tsp_common_int_handler` in addition to 0 (interrupt successfully handled) and in both cases it issues an SMC with id `TSP_HANDLED_S_EL1_INTR`. The TSPD switches the context and returns back to normal world. In case a higher priority EL3 interrupt was pending, the execution will be routed to EL3 where interrupt will be handled. On return back to normal world, the pending S-EL1 interrupt which was preempted will get routed to S-EL1 to be handled `synchronously` via `tsp_sel1_intr_entry`. Change-Id: I2087c7fedb37746fbd9200cdda9b6dba93e16201		2015-12-09 09:58:17 +00:00
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tsp_entrypoint.S	TSP: Allow preemption of synchronous S-EL1 interrupt handling	2015-12-09 09:58:17 +00:00
tsp_exceptions.S	Enable use of FIQs and IRQs as TSP interrupts	2015-12-04 12:02:12 +00:00
tsp_request.S	Add support to indicate size and end of assembly functions	2015-04-08 13:02:59 +01:00