Caesar Wang dea1e8ee80 rockchip: enable A53's erratum 855873 for rk3399 ... For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't support WriteEvict. and you will hit the condition L2ACTLR[3] with 0, as the Evict transactions should propagate to CCI-500 since it has snoop filters. Maybe this erratum applies to all Cortex-A53 cores so far, especially if RK3399's A53 is a r0p4. we should enable it to avoid data corruption, Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f Signed-off-by: Caesar Wang <wxt@rock-chips.com>		2017-06-28 08:40:26 +08:00
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drivers	rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend	2017-06-08 09:59:53 +08:00
include	rockchip: check wakeup cpu when resume	2017-06-08 10:01:19 +08:00
plat_sip_calls.c	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
platform.mk	rockchip: enable A53's erratum 855873 for rk3399	2017-06-28 08:40:26 +08:00
rk3399_def.h	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00