Hadi Asyrafi fea24b88e4 intel: stratix10: Fix reliance on hard coded clock information ... Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03		2019-08-13 18:20:53 +08:00
..
include	intel: stratix10: Fix reliance on hard coded clock information	2019-08-13 18:20:53 +08:00
soc	intel: stratix10: Fix reliance on hard coded clock information	2019-08-13 18:20:53 +08:00
bl2_plat_setup.c	intel: stratix10: Fix reliance on hard coded clock information	2019-08-13 18:20:53 +08:00
bl31_plat_setup.c	Merge changes from topic "intel-plat-refactor" into integration	2019-08-07 14:20:01 +00:00
plat_psci.c	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
plat_sip_svc.c	plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform	2019-02-26 09:25:14 +08:00
plat_storage.c	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
platform.mk	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00