Completed expanding formatting
This commit is contained in:
Jeremiah Orians
parent
ac26fcc22c
commit
002e6f8693
525
ISA_HEX_Map.org
525
ISA_HEX_Map.org
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@ -46,9 +46,11 @@
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| 01 13 ab cd | SORTU a b c d | a = MAX(c, d); b = MIN(c, d) [unsigned] |
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| 01 13 ab cd | SORTU a b c d | a = MAX(c, d); b = MIN(c, d) [unsigned] |
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**** Reserved Block
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**** Reserved Block
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01 14 xx xx # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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01 FF xx xx # Reserved
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| 01 14 xx xx | Reserved |
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| ... | Reserved |
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| 01 FF xx xx | Reserved |
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*** 02 nn ab cd :: 4OP Floating group
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*** 02 nn ab cd :: 4OP Floating group
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*** 03 nn ab cd :: 4OP SIMD group
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*** 03 nn ab cd :: 4OP SIMD group
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@ -58,106 +60,128 @@
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3OP nn n is the XOP, a = b OP c
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3OP nn n is the XOP, a = b OP c
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*** 05 nn na bc :: 3OP Integer group
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*** 05 nn na bc :: 3OP Integer group
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**** Turing group
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**** Turing group
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05 00 0a bc # ADD a b c :: a = b + c [signed]
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| Hex | Name | Comment |
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05 00 1a bc # ADDU a b c :: a = b + c [unsigned]
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|-------------+------------+------------------------|
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05 00 2a bc # SUB a b c :: a = b - c [signed]
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| 05 00 0a bc | ADD a b c | a = b + c [signed] |
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05 00 3a bc # SUBU a b c :: a = b - c [unsigned]
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| 05 00 1a bc | ADDU a b c | a = b + c [unsigned] |
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05 00 4a bc # CMP a b c :: a = b CMP c [signed]
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| 05 00 2a bc | SUB a b c | a = b - c [signed] |
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05 00 5a bc # CMPU a b c :: a = b CMP c [unsigned]
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| 05 00 3a bc | SUBU a b c | a = b - c [unsigned] |
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| 05 00 4a bc | CMP a b c | a = b CMP c [signed] |
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| 05 00 5a bc | CMPU a b c | a = b CMP c [unsigned] |
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**** Convience group
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**** Convience group
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05 00 6a bc # MUL a b c :: a = b * c [signed] bottom n bits
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| Hex | Name | Comment |
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05 00 7a bc # MULH a b c :: a = (b * c) >> n [signed] top n bits
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|-------------+-------------+----------------------------------------|
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05 00 8a bc # MULU a b c :: a = b * c [unsigned] bottom n bits
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| 05 00 6a bc | MUL a b c | a = b * c [signed] bottom n bits |
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05 00 9a bc # MULUH a b c :: a = (b * c) >> n [unsigned] top n bits
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| 05 00 7a bc | MULH a b c | a = (b * c) >> n [signed] top n bits |
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05 00 Aa bc # DIV a b c :: a = b / c [signed]
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| 05 00 8a bc | MULU a b c | a = b * c [unsigned] bottom n bits |
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05 00 Ba bc # MOD a b c :: a = b % c [signed]
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| 05 00 9a bc | MULUH a b c | a = (b * c) >> n [unsigned] top n bits |
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05 00 Ca bc # DIVU a b c :: a = b / c [unsigned]
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| 05 00 Aa bc | DIV a b c | a = b / c [signed] |
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05 00 Da bc # MODU a b c :: a = b % c [unsigned]
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| 05 00 Ba bc | MOD a b c | a = b % c [signed] |
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| 05 00 Ca bc | DIVU a b c | a = b / c [unsigned] |
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| 05 00 Da bc | MODU a b c | a = b % c [unsigned] |
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**** Reserved group 0
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**** Reserved group 0
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05 00 Ex xx # Reserved
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| Hex | Name |
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05 00 Fx xx # Reserved
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|-------------+----------|
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| 05 00 Ex xx | Reserved |
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| 05 00 Fx xx | Reserved |
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**** Sort group
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**** Sort group
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05 01 0a bc # MAX a b c :: a = MAX(b, c) [signed]
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| Hex | Name | Comment |
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05 01 1a bc # MAXU a b c :: a = MAX(b, c) [unsigned]
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|-------------+------------+--------------------------|
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05 01 2a bc # MIN a b c :: a = MIN(b, c) [signed]
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| 05 01 0a bc | MAX a b c | a = MAX(b, c) [signed] |
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05 01 3a bc # MINU a b c :: a = MIN(b, c) [unsigned]
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| 05 01 1a bc | MAXU a b c | a = MAX(b, c) [unsigned] |
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| 05 01 2a bc | MIN a b c | a = MIN(b, c) [signed] |
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| 05 01 3a bc | MINU a b c | a = MIN(b, c) [unsigned] |
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**** Binary packing group
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**** Binary packing group
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05 01 4a bc # PACK a b c :: a = PACK(b, c)
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| Hex | Name | Comment |
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05 01 5a bc # UNPACK a b c :: a = UNPACK(b, c)
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|-------------+------------------+--------------------------------------|
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05 01 6a bc # PACK8.CO a b c :: a = PACK(b) c = Overload? [signed]
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| 05 01 4a bc | PACK a b c | a = PACK(b, c) |
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05 01 7a bc # PACK8U.CO a b c :: a = PACK(b) c = Overload? [unsigned]
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| 05 01 5a bc | UNPACK a b c | a = UNPACK(b, c) |
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05 01 8a bc # PACK16.CO a b c :: a = PACK(b) c = Overload? [signed]
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| 05 01 6a bc | PACK8.CO a b c | a = PACK(b) c = Overload? [signed] |
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05 01 9a bc # PACK16U.CO a b c :: a = PACK(b) c = Overload? [unsigned]
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| 05 01 7a bc | PACK8U.CO a b c | a = PACK(b) c = Overload? [unsigned] |
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05 01 Aa bc # PACK32.CO a b c :: a = PACK(b) c = Overload? [signed]
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| 05 01 8a bc | PACK16.CO a b c | a = PACK(b) c = Overload? [signed] |
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05 01 Ba bc # PACK32U.CO a b c :: a = PACK(b) c = Overload? [unsigned]
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| 05 01 9a bc | PACK16U.CO a b c | a = PACK(b) c = Overload? [unsigned] |
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05 01 Ca bc # Reserved
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| 05 01 Aa bc | PACK32.CO a b c | a = PACK(b) c = Overload? [signed] |
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05 01 Da bc # Reserved
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| 05 01 Ba bc | PACK32U.CO a b c | a = PACK(b) c = Overload? [unsigned] |
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05 01 Ex xx # Reserved
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| 05 01 Ca bc | Reserved | |
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05 01 Fx xx # Reserved
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| 05 01 Da bc | Reserved | |
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| 05 01 Ex xx | Reserved | |
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| 05 01 Fx xx | Reserved | |
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**** Logical group
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**** Logical group
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05 02 0a bc # AND a b c :: a = b & c
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| Hex | Name | Comment |
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05 02 1a bc # OR a b c :: a = b | c
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|-------------+------------+---------------------------------------|
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05 02 2a bc # XOR a b c :: a = b XOR c
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| 05 02 0a bc | AND a b c | a = b & c |
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05 02 3a bc # NAND a b c :: a != b & c
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| 05 02 1a bc | OR a b c | a = b \vert c |
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05 02 4a bc # NOR a b c :: a != b | c
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| 05 02 2a bc | XOR a b c | a = b XOR c |
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05 02 5a bc # XNOR a b c :: a != b XOR c
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| 05 02 3a bc | NAND a b c | a != b & c |
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05 02 6a bc # MPQ a b c :: a = b MPQ c [Converse Nonimplication]
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| 05 02 4a bc | NOR a b c | a != b \vert c |
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05 02 7a bc # LPQ a b c :: a = b LPQ c [Material Nonimplication]
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| 05 02 5a bc | XNOR a b c | a != b XOR c |
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05 02 8a bc # CPQ a b c :: a = b CPQ c [Material Implication]
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| 05 02 6a bc | MPQ a b c | a = b MPQ c [Converse Nonimplication] |
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05 02 9a bc # BPQ a b c :: a = b BPQ c [Converse Implication]
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| 05 02 7a bc | LPQ a b c | a = b LPQ c [Material Nonimplication] |
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| 05 02 8a bc | CPQ a b c | a = b CPQ c [Material Implication] |
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| 05 02 9a bc | BPQ a b c | a = b BPQ c [Converse Implication] |
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**** Reserved group 1
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**** Reserved group 1
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05 02 Ax xx # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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05 02 Fx xx # Reserved
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| 05 02 Ax xx | Reserved |
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| ... | Reserved |
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| 05 02 Fx xx | Reserved |
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**** Bit rotation group
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**** Bit rotation group
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05 03 0a bc # SAL a b c :: a = b << c [arithmetically]
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| Hex | Name | Comment |
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05 03 1a bc # SAR a b c :: a = b >> c [arithmetically]
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|-------------+-----------+---------------------------------------|
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05 03 2a bc # SL0 a b c :: a = b << c [Fill with zeros]
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| 05 03 0a bc | SAL a b c | a = b << c [arithmetically] |
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05 03 3a bc # SR0 a b c :: a = b >> c [Fill with zeros]
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| 05 03 1a bc | SAR a b c | a = b >> c [arithmetically] |
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05 03 4a bc # SL1 a b c :: a = b << c [Fill with ones]
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| 05 03 2a bc | SL0 a b c | a = b << c [Fill with zeros] |
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05 03 5a bc # SR1 a b c :: a = b >> c [Fill with ones]
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| 05 03 3a bc | SR0 a b c | a = b >> c [Fill with zeros] |
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05 03 6a bc # ROL a b c :: a = ROL(b, c) [Circular rotate left]
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| 05 03 4a bc | SL1 a b c | a = b << c [Fill with ones] |
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05 03 7a bc # ROR a b c :: a = ROR(b, c) [Circular rotate right]
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| 05 03 5a bc | SR1 a b c | a = b >> c [Fill with ones] |
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| 05 03 6a bc | ROL a b c | a = ROL(b, c) [Circular rotate left] |
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| 05 03 7a bc | ROR a b c | a = ROR(b, c) [Circular rotate right] |
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**** Load group
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**** Load group
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05 03 8a bc # LOADX a b c :: a = MEM[b+c]
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| Hex | Name | Comment |
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05 03 9a bc # LOADX8 a b c :: a = MEM[b+c] [signed 8bits]
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|-------------+----------------+--------------------------------|
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05 03 Aa bc # LOADXU8 a b c :: a = MEM[b+c] [unsigned 8bits]
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| 05 03 8a bc | LOADX a b c | a = MEM[b+c] |
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05 03 Ba bc # LOADX16 a b c :: a = MEM[b+c] [signed 16bits]
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| 05 03 9a bc | LOADX8 a b c | a = MEM[b+c] [signed 8bits] |
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05 03 Ca bc # LOADXU16 a b c :: a = MEM[b+c] [unsigned 16bits]
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| 05 03 Aa bc | LOADXU8 a b c | a = MEM[b+c] [unsigned 8bits] |
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05 03 Da bc # LOADX32 a b c :: a = MEM[b+c] [signed 32bits]
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| 05 03 Ba bc | LOADX16 a b c | a = MEM[b+c] [signed 16bits] |
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05 03 Ea bc # LOADXU32 a b c :: a = MEM[b+c] [unsigned 32bits]
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| 05 03 Ca bc | LOADXU16 a b c | a = MEM[b+c] [unsigned 16bits] |
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05 03 Fx xx # Reserved
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| 05 03 Da bc | LOADX32 a b c | a = MEM[b+c] [signed 32bits] |
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05 04 0x xx # Reserved
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| 05 03 Ea bc | LOADXU32 a b c | a = MEM[b+c] [unsigned 32bits] |
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05 04 1x xx # Reserved
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| 05 03 Fx xx | Reserved | |
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05 04 2x xx # Reserved
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| 05 04 0x xx | Reserved | |
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05 04 3x xx # Reserved
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| 05 04 1x xx | Reserved | |
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05 04 4x xx # Reserved
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| 05 04 2x xx | Reserved | |
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05 04 5x xx # Reserved
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| 05 04 3x xx | Reserved | |
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05 04 6x xx # Reserved
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| 05 04 4x xx | Reserved | |
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05 04 7x xx # Reserved
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| 05 04 5x xx | Reserved | |
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| 05 04 6x xx | Reserved | |
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| 05 04 7x xx | Reserved | |
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**** Store group
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**** Store group
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05 04 8a bc # STOREX a b c :: MEM[b+c] = a
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| Hex | Name | Comment |
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05 04 9a bc # STOREX8 a b c :: MEM[b+c] = a [8bits]
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|-------------+----------------+-----------------------|
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05 04 Aa bc # STOREX16 a b c :: MEM[b+c] = a [16bits]
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| 05 04 8a bc | STOREX a b c | MEM[b+c] = a |
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05 04 Ba bc # STOREX32 a b c :: MEM[b+c] = a [32bits]
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| 05 04 9a bc | STOREX8 a b c | MEM[b+c] = a [8bits] |
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05 04 Cx xx # Reserved
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| 05 04 Aa bc | STOREX16 a b c | MEM[b+c] = a [16bits] |
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05 04 Dx xx # Reserved
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| 05 04 Ba bc | STOREX32 a b c | MEM[b+c] = a [32bits] |
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05 04 Ex xx # Reserved
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| 05 04 Cx xx | Reserved | |
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05 04 Fx xx # Reserved
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| 05 04 Dx xx | Reserved | |
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| 05 04 Ex xx | Reserved | |
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| 05 04 Fx xx | Reserved | |
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**** Reserved group 2
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**** Reserved group 2
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05 05 0x xx # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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05 FF Fx xx # Reserved
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| 05 05 0x xx | Reserved |
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| ... | Reserved |
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| 05 FF Fx xx | Reserved |
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*** 06 nn na bc :: 3OP Floating group
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*** 06 nn na bc :: 3OP Floating group
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*** 07 nn na bc :: 3OP SIMD group
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*** 07 nn na bc :: 3OP SIMD group
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@ -167,28 +191,39 @@
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2OP nn nn is the XOP, a = OP b
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2OP nn nn is the XOP, a = OP b
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*** 09 nn nn ab :: 2OP Integer group
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*** 09 nn nn ab :: 2OP Integer group
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**** Numeric subgroup
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**** Numeric group
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09 00 00 ab # NEG a b :: a = (b > 0) ? -b : b
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| Hex | Name | Comment |
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09 00 01 ab # ABS a b :: a = |b|
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|-------------+----------+----------------------|
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09 00 02 ab # NABS a b :: a = -|b|
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| 09 00 00 ab | NEG a b | a = (b > 0) ? -b : b |
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| 09 00 01 ab | ABS a b | a = \vert b \vert |
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| 09 00 02 ab | NABS a b | a = - \vert b \vert |
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**** Movement subgroup
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**** Movement group
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09 00 03 ab # SWAP a b :: a <=> b
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| Hex | Name | Comment |
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09 00 04 ab # COPY a b :: a = b
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|-------------+----------+--------------|
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09 00 05 ab # MOVE a b :: a = b; b = 0
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| 09 00 03 ab | SWAP a b | a <=> b |
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| 09 00 04 ab | COPY a b | a = b |
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| 09 00 05 ab | MOVE a b | a = b; b = 0 |
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**** Reserved Block 0
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**** Reserved Block 0
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09 00 06 xx # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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09 00 FF xx # Reserved
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| 09 00 06 xx | Reserved |
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| ... | Reserved |
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| 09 00 FF xx | Reserved |
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**** Function call group
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| Hex | Name | Comment |
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|-------------+------------+-------------------------------------------------------|
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| 09 01 00 ab | BRANCH a b | MEM[b] = PC; PC = a |
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| 09 01 01 ab | CALL a b | MEM[b] = PC; b = b + (register size in bytes); PC = a |
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**** Function call subgroup
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09 01 00 ab # BRANCH a b :: MEM[b] = PC; PC = a
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09 01 01 ab # CALL a b :: MEM[b] = PC; b = b + (register size in bytes); PC = a
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**** Reserved Block 1
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**** Reserved Block 1
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09 01 02 xx # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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09 FF FF xx # Reserved
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| 09 01 02 xx | Reserved |
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| ... | Reserved |
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| 09 FF FF xx | Reserved |
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*** 0A nn nn ab :: 2OP Floating group
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*** 0A nn nn ab :: 2OP Floating group
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*** 0B nn nn ab :: 2OP SIMD group
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*** 0B nn nn ab :: 2OP SIMD group
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@ -198,131 +233,165 @@
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1OP nn nn n is the XOP, a = OP a
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1OP nn nn n is the XOP, a = OP a
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*** 0D nn nn na :: 1OP group
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*** 0D nn nn na :: 1OP group
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**** State subgroup
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**** State group
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0D 00 00 0a # READPC a :: a = PC
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| Hex | Name | Comment |
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0D 00 00 1a # READSCID a :: a = SCID
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|-------------+------------+---------------|
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0D 00 00 2a # FALSE a :: a = 0
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| 0D 00 00 0a | READPC a | a = PC |
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0D 00 00 3a # TRUE a :: a = FF ... FF
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| 0D 00 00 1a | READSCID a | a = SCID |
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| 0D 00 00 2a | FALSE a | a = 0 |
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| 0D 00 00 3a | TRUE a | a = FF ... FF |
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**** Reserved block 0
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**** Reserved block 0
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0D 00 00 4x # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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0D 00 FF Fx # Reserved
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| 0D 00 00 4x | Reserved |
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| ... | Reserved |
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| 0D 00 FF Fx | Reserved |
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**** Function return subgroup
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**** Function return group
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0D 01 00 0a # JSR_COROUTINE a; PC = a
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| Hex | Name | Comment |
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0D 01 00 1a # RET a :: PC = MEM[a]; a = a - (register size in bytes)
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|-------------+-----------------+-----------------------------------------------|
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| 0D 01 00 0a | JSR_COROUTINE a | PC = a |
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| 0D 01 00 1a | RET a | PC = MEM[a]; a = a - (register size in bytes) |
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**** Reserved block 1
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**** Reserved block 1
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0D 01 00 2x # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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0D 01 FF Fx # Reserved
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| 0D 01 00 2x | Reserved |
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| ... | Reserved |
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| 0D 01 FF Fx | Reserved |
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**** Stack state Subgroup
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**** Stack state group
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0D 02 00 0a # PUSHPC a :: MEM[a] = PC; a = a + (register size in bytes)
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| Hex | Name | Comment |
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0D 02 00 1a # POPPC a :: PC = MEM[a]; a = a - (register size in bytes)
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|-------------+----------+-----------------------------------------------|
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| 0D 02 00 0a | PUSHPC a | MEM[a] = PC; a = a + (register size in bytes) |
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| 0D 02 00 1a | POPPC a | PC = MEM[a]; a = a - (register size in bytes) |
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**** Reserved
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**** Reserved
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0D 02 00 2x # Reserved
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| Hex | Name |
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...
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|-------------+----------|
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0D FF FF Fx # Reserved
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| 0D 02 00 2x | Reserved |
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| ... | Reserved |
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| 0D FF FF Fx | Reserved |
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** 2OPI Groups
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** 2OPI Groups
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2OPI ii ii is the Immediate, a = b OP ii ii
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2OPI ii ii is the Immediate, a = b OP ii ii
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*** 2OPI Integer
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*** 2OPI Integer
|
||||||
0E ab ii ii # ADDI a b ii ii :: a = b + ii ii [signed]
|
| Hex | Name | Comment |
|
||||||
0F ab ii ii # ADDUI a b ii ii :: a = b + ii ii [unsigned]
|
|-------------+-----------------+--------------------------|
|
||||||
10 ab ii ii # SUBI a b ii ii :: a = b - ii ii [signed]
|
| 0E ab ii ii | ADDI a b ii ii | a = b + ii ii [signed] |
|
||||||
11 ab ii ii # SUBUI a b ii ii :: a = b - ii ii [unsigned]
|
| 0F ab ii ii | ADDUI a b ii ii | a = b + ii ii [unsigned] |
|
||||||
|
| 10 ab ii ii | SUBI a b ii ii | a = b - ii ii [signed] |
|
||||||
|
| 11 ab ii ii | SUBUI a b ii ii | a = b - ii ii [unsigned] |
|
||||||
|
|
||||||
*** 2OPI Integer signed compare
|
*** 2OPI Integer signed compare
|
||||||
12 ab ii ii # CMPI a b ii ii :: a = b CMP ii ii [signed]
|
| Hex | Name | Comment |
|
||||||
|
|-------------+----------------+--------------------------|
|
||||||
|
| 12 ab ii ii | CMPI a b ii ii | a = b CMP ii ii [signed] |
|
||||||
|
|
||||||
*** 2OPI Integer Load
|
*** 2OPI Integer Load
|
||||||
13 ab ii ii # LOAD a b ii ii :: a = MEM[b + ii ii]
|
| Hex | Name | Comment |
|
||||||
14 ab ii ii # LOAD8 a b ii ii :: a = MEM[b + ii ii] [signed 8bits]
|
|-------------+-------------------+--------------------------------------|
|
||||||
15 ab ii ii # LOADU8 a b ii ii :: a = MEM[b + ii ii] [unsigned 8bits]
|
| 13 ab ii ii | LOAD a b ii ii | a = MEM[b + ii ii] |
|
||||||
16 ab ii ii # LOAD16 a b ii ii :: a = MEM[b + ii ii] [signed 16bits]
|
| 14 ab ii ii | LOAD8 a b ii ii | a = MEM[b + ii ii] [signed 8bits] |
|
||||||
17 ab ii ii # LOADU16 a b ii ii :: a = MEM[b + ii ii] [unsigned 16bits]
|
| 15 ab ii ii | LOADU8 a b ii ii | a = MEM[b + ii ii] [unsigned 8bits] |
|
||||||
18 ab ii ii # LOAD32 a b ii ii :: a = MEM[b + ii ii] [signed 32bits]
|
| 16 ab ii ii | LOAD16 a b ii ii | a = MEM[b + ii ii] [signed 16bits] |
|
||||||
19 ab ii ii # LOADU32 a b ii ii :: a = MEM[b + ii ii] [unsigned 32bits]
|
| 17 ab ii ii | LOADU16 a b ii ii | a = MEM[b + ii ii] [unsigned 16bits] |
|
||||||
1A ab ii ii # Reserved
|
| 18 ab ii ii | LOAD32 a b ii ii | a = MEM[b + ii ii] [signed 32bits] |
|
||||||
1B ab ii ii # Reserved
|
| 19 ab ii ii | LOADU32 a b ii ii | a = MEM[b + ii ii] [unsigned 32bits] |
|
||||||
1C ab ii ii # Reserved
|
| 1A ab ii ii | Reserved | |
|
||||||
1D ab ii ii # Reserved
|
| 1B ab ii ii | Reserved | |
|
||||||
1E ab ii ii # Reserved
|
| 1C ab ii ii | Reserved | |
|
||||||
|
| 1D ab ii ii | Reserved | |
|
||||||
|
| 1E ab ii ii | Reserved | |
|
||||||
|
|
||||||
*** 2OPI Integer unsigned compare
|
*** 2OPI Integer unsigned compare
|
||||||
1F ab ii ii # CMPUI a b ii ii :: a = b CMP ii ii [unsigned]
|
| Hex | Name | Comment |
|
||||||
|
|-------------+-----------------+----------------------------|
|
||||||
|
| 1F ab ii ii | CMPUI a b ii ii | a = b CMP ii ii [unsigned] |
|
||||||
|
|
||||||
*** 2OPI Integer store
|
*** 2OPI Integer store
|
||||||
20 ab ii ii # STORE a b ii :: MEM[b + ii ii] = a
|
| Hex | Name | Comment |
|
||||||
21 ab ii ii # STORE8 a b ii :: MEM[b + ii ii] = a [signed 8bits]
|
|-------------+----------------+------------------------------------|
|
||||||
22 ab ii ii # STORE16 a b ii :: MEM[b + ii ii] = a [signed 16bits]
|
| 20 ab ii ii | STORE a b ii | MEM[b + ii ii] = a |
|
||||||
23 ab ii ii # STORE32 a b ii :: MEM[b + ii ii] = a [signed 32bits]
|
| 21 ab ii ii | STORE8 a b ii | MEM[b + ii ii] = a [signed 8bits] |
|
||||||
24 ab ii ii # Reserved
|
| 22 ab ii ii | STORE16 a b ii | MEM[b + ii ii] = a [signed 16bits] |
|
||||||
25 ab ii ii # Reserved
|
| 23 ab ii ii | STORE32 a b ii | MEM[b + ii ii] = a [signed 32bits] |
|
||||||
26 ab ii ii # Reserved
|
| 24 ab ii ii | Reserved | |
|
||||||
27 ab ii ii # Reserved
|
| 25 ab ii ii | Reserved | |
|
||||||
28 ab ii ii # Reserved
|
| 26 ab ii ii | Reserved | |
|
||||||
29 ab ii ii # Reserved
|
| 27 ab ii ii | Reserved | |
|
||||||
2A ab ii ii # Reserved
|
| 28 ab ii ii | Reserved | |
|
||||||
2B ab ii ii # Reserved
|
| 29 ab ii ii | Reserved | |
|
||||||
|
| 2A ab ii ii | Reserved | |
|
||||||
|
| 2B ab ii ii | Reserved | |
|
||||||
|
|
||||||
** 1OPI Groups
|
** 1OPI Groups
|
||||||
1OPI i ii ii is the Immediate, a = a OP i ii ii
|
1OPI i ii ii is the Immediate, a = a OP i ii ii
|
||||||
|
|
||||||
*** Conditional Integer Jumps
|
*** Conditional Integer Jumps
|
||||||
2C 0a ii ii # JUMP.C a ii ii :: Carry? a; PC = PC + i ii ii
|
| Hex | Name | Comment |
|
||||||
2C 1a ii ii # JUMP.B a ii ii :: Borrow? a; PC = PC + i ii ii
|
|-------------+-----------------+--------------------------------------|
|
||||||
2C 2a ii ii # JUMP.O a ii ii :: Overflow? a; PC = PC + i ii ii
|
| 2C 0a ii ii | JUMP.C a ii ii | Carry? a; PC = PC + i ii ii |
|
||||||
2C 3a ii ii # JUMP.G a ii ii :: GT? a; PC = PC + i ii ii
|
| 2C 1a ii ii | JUMP.B a ii ii | Borrow? a; PC = PC + i ii ii |
|
||||||
2C 4a ii ii # JUMP.GE a ii ii :: GT? a | EQ? a; PC = PC + i ii ii
|
| 2C 2a ii ii | JUMP.O a ii ii | Overflow? a; PC = PC + i ii ii |
|
||||||
2C 5a ii ii # JUMP.E a ii ii :: EQ? a; PC = PC + i ii ii
|
| 2C 3a ii ii | JUMP.G a ii ii | GT? a; PC = PC + i ii ii |
|
||||||
2C 6a ii ii # JUMP.NE a ii ii :: NEQ? a; PC = PC + i ii ii
|
| 2C 4a ii ii | JUMP.GE a ii ii | GT? a \vert EQ? a; PC = PC + i ii ii |
|
||||||
2C 7a ii ii # JUMP.LE a ii ii :: LT? a | EQ? a; PC = PC + i ii ii
|
| 2C 5a ii ii | JUMP.E a ii ii | EQ? a; PC = PC + i ii ii |
|
||||||
2C 8a ii ii # JUMP.L a ii ii :: LT? a; PC = PC + i ii ii
|
| 2C 6a ii ii | JUMP.NE a ii ii | NEQ? a; PC = PC + i ii ii |
|
||||||
2C 9a ii ii # JUMP.Z a ii ii :: ZERO? a; PC = PC + i ii ii
|
| 2C 7a ii ii | JUMP.LE a ii ii | LT? a \vert EQ? a; PC = PC + i ii ii |
|
||||||
2C Aa ii ii # JUMP.NZ a ii ii :: NZERO? a; PC = PC + i ii ii
|
| 2C 8a ii ii | JUMP.L a ii ii | LT? a; PC = PC + i ii ii |
|
||||||
2C Bx xx xx # Reserved
|
| 2C 9a ii ii | JUMP.Z a ii ii | ZERO? a; PC = PC + i ii ii |
|
||||||
2C Cx xx xx # Reserved
|
| 2C Aa ii ii | JUMP.NZ a ii ii | NZERO? a; PC = PC + i ii ii |
|
||||||
2C Dx xx xx # Reserved
|
| 2C Bx xx xx | Reserved | |
|
||||||
2C Ex xx xx # Reserved
|
| 2C Cx xx xx | Reserved | |
|
||||||
2C Fx xx xx # Reserved
|
| 2C Dx xx xx | Reserved | |
|
||||||
|
| 2C Ex xx xx | Reserved | |
|
||||||
|
| 2C Fx xx xx | Reserved | |
|
||||||
|
|
||||||
*** Branch Immediates
|
*** Branch Immediates
|
||||||
2D 0a ii ii # CALLI a ii ii :: MEM[a] = PC; a = a + (register size in bytes); PC = PC + ii ii
|
| Hex | Name | Comment |
|
||||||
2D 1a ii ii # LOADI a ii ii :: a = ii ii (signed)
|
|-------------+----------------+----------------------------------------------------------------|
|
||||||
2D 2a ii ii # LOADUI a ii ii :: a = ii ii (unsigned)
|
| 2D 0a ii ii | CALLI a ii ii | MEM[a] = PC; a = a + (register size in bytes); PC = PC + ii ii |
|
||||||
2D 3a ii ii # SALI a ii ii :: a = a << ii ii [arithmetically]
|
| 2D 1a ii ii | LOADI a ii ii | a = ii ii (signed) |
|
||||||
2D 4a ii ii # SARI a ii ii :: a = a >> ii ii [arithmetically]
|
| 2D 2a ii ii | LOADUI a ii ii | a = ii ii (unsigned) |
|
||||||
2D 5a ii ii # SL0I a ii ii :: a = a << ii ii [Fill with zeros]
|
| 2D 3a ii ii | SALI a ii ii | a = a << ii ii [arithmetically] |
|
||||||
2D 6a ii ii # SR0I a ii ii :: a = a >> ii ii [Fill with zeros]
|
| 2D 4a ii ii | SARI a ii ii | a = a >> ii ii [arithmetically] |
|
||||||
2D 7a ii ii # SL1I a ii ii :: a = a << ii ii [Fill with ones]
|
| 2D 5a ii ii | SL0I a ii ii | a = a << ii ii [Fill with zeros] |
|
||||||
2D 8a ii ii # SR1I a ii ii :: a = a >> ii ii [Fill with ones]
|
| 2D 6a ii ii | SR0I a ii ii | a = a >> ii ii [Fill with zeros] |
|
||||||
|
| 2D 7a ii ii | SL1I a ii ii | a = a << ii ii [Fill with ones] |
|
||||||
|
| 2D 8a ii ii | SR1I a ii ii | a = a >> ii ii [Fill with ones] |
|
||||||
|
|
||||||
** 0OPI group
|
** 0OPI group
|
||||||
0OPI ii ii is the Immediate, OP ii ii
|
0OPI ii ii is the Immediate, OP ii ii
|
||||||
|
|
||||||
*** Unconditional jumps
|
*** Unconditional jumps
|
||||||
3C 00 ii ii # JUMP ii ii :: PC = PC + ii ii
|
| Hex | Name | Comment |
|
||||||
|
|-------------+------------+-----------------|
|
||||||
|
| 3C 00 ii ii | JUMP ii ii | PC = PC + ii ii |
|
||||||
|
|
||||||
** Reserved Block 0
|
** Reserved Block 0
|
||||||
At this time these instructions only produce a warning; but could do anything.
|
At this time these instructions only produce a warning; but could do anything.
|
||||||
DO NOT USE.
|
DO NOT USE.
|
||||||
3D 00 00 00 # Reserved
|
|
||||||
...
|
| Hex | Name |
|
||||||
41 FF FF FF # Reserve
|
|-------------+----------|
|
||||||
|
| 3D 00 00 00 | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| 41 FF FF FF | Reserve |
|
||||||
|
|
||||||
** HALCODE Group
|
** HALCODE Group
|
||||||
42 hh hh hh is the HALCODE callID, invalid HALCODE SHOULD NOT BE USED.
|
42 hh hh hh is the HALCODE callID, invalid HALCODE SHOULD NOT BE USED.
|
||||||
|
|
||||||
*** HALCODE Reserved for Operating Systems
|
*** HALCODE Reserved for Operating Systems
|
||||||
The following block contains both instructions that are reserved for Operating systems and for internal use by Operating systems
|
The following block contains both instructions that are reserved for Operating systems and for internal use by Operating systems
|
||||||
42 00 xx xx # Reserved
|
|
||||||
...
|
| Hex | Name |
|
||||||
42 0F xx xx # Reserved
|
|-------------+----------|
|
||||||
|
| 42 00 xx xx | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| 42 0F xx xx | Reserved |
|
||||||
|
|
||||||
*** Tape console HALCODE
|
*** Tape console HALCODE
|
||||||
This HALCODE is used for interacting with any tape console attached to the system.
|
This HALCODE is used for interacting with any tape console attached to the system.
|
||||||
|
|
@ -335,54 +404,92 @@ Padding with Zeros til start/end of page/segment however is acceptable.
|
||||||
|
|
||||||
**** Standard compatibility requirements
|
**** Standard compatibility requirements
|
||||||
The following 3 devices must exist with the following exact IDs
|
The following 3 devices must exist with the following exact IDs
|
||||||
Keyboard/tty :: 00 00 00 00
|
| Interface Name | ID |
|
||||||
Tape 1 :: 00 00 11 00
|
|----------------+-------------|
|
||||||
Tape 2 :: 00 00 11 01
|
| Keyboard/tty | 00 00 00 00 |
|
||||||
|
| Tape 1 | 00 00 11 00 |
|
||||||
|
| Tape 2 | 00 00 11 01 |
|
||||||
|
|
||||||
**** Required Device HALCODE
|
**** Required Device HALCODE
|
||||||
42 10 00 00 # FOPEN :: Feed on device who's ID matches the contents register 0 until first non-zero byte is found.
|
| Hex | Name | Comment |
|
||||||
42 10 00 01 # FCLOSE :: Close out writes to device who's ID matches the contents of register 0.
|
|-------------+--------+----------------------------------------------------------------------------------------------------------------------------------|
|
||||||
42 10 00 02 # FSEEK :: seek forward or backward the number of bytes specified in register 1 on the device who's ID matches the contents of register 0.
|
| 42 10 00 00 | FOPEN | Feed on device who's ID matches the contents register 0 until first non-zero byte is found. |
|
||||||
42 10 00 03 # REWIND :: rewind back to first non-zero byte found on tape.
|
| 42 10 00 01 | FCLOSE | Close out writes to device who's ID matches the contents of register 0. |
|
||||||
|
| 42 10 00 02 | FSEEK | seek forward or backward the number of bytes specified in register 1 on the device who's ID matches the contents of register 0. |
|
||||||
|
| 42 10 00 03 | REWIND | rewind back to first non-zero byte found on tape. |
|
||||||
|
|
||||||
**** Reserved Block for Hardware specific implementation details
|
**** Reserved Block for Hardware specific implementation details
|
||||||
42 10 00 04 # Reserved
|
| Hex | Name |
|
||||||
...
|
|-------------+----------|
|
||||||
42 10 00 FF # Reserved
|
| 42 10 00 04 | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| 42 10 00 FF | Reserved |
|
||||||
|
|
||||||
**** Required Device capability HALCODE
|
**** Required Device capability HALCODE
|
||||||
***** Device Read HALCODE
|
***** Device Read HALCODE
|
||||||
42 10 01 00 # FGETC :: read 1 byte into register 0 from device who's ID is in register 1
|
| Hex | Name | Comment |
|
||||||
|
|-------------+-------+-------------------------------------------------------------------|
|
||||||
|
| 42 10 01 00 | FGETC | read 1 byte into register 0 from device who's ID is in register 1 |
|
||||||
|
|
||||||
***** Reserved Block for Hardware specific implementation details
|
***** Reserved Block for Hardware specific implementation details
|
||||||
42 10 01 01 # Reserved
|
| Hex | Name |
|
||||||
...
|
|-------------+----------|
|
||||||
42 10 01 FF # Reserved
|
| 42 10 01 01 | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| 42 10 01 FF | Reserved |
|
||||||
|
|
||||||
***** Device Write HALCODE
|
***** Device Write HALCODE
|
||||||
42 10 02 00 # FPUTC :: write 1 byte from register 0 to device who's ID is in register 1
|
| Hex | Name | Comment |
|
||||||
|
|-------------+-------+------------------------------------------------------------------|
|
||||||
|
| 42 10 02 00 | FPUTC | write 1 byte from register 0 to device who's ID is in register 1 |
|
||||||
|
|
||||||
***** Reserved Block for Hardware specific implementation details
|
***** Reserved Block for Hardware specific implementation details
|
||||||
42 10 02 01 # Reserved
|
| Hex | Name |
|
||||||
...
|
|-------------+----------|
|
||||||
42 10 02 FF # Reserved
|
| 42 10 02 01 | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| 42 10 02 FF | Reserved |
|
||||||
|
|
||||||
**** Reserved Block for Future HALCODE Expansion
|
**** Reserved Block for Future HALCODE Expansion
|
||||||
42 10 03 00 # Reserved
|
| Hex | Name |
|
||||||
...
|
|-------------+----------|
|
||||||
42 FF FF FF # Reserved
|
| 42 10 03 00 | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| 42 FF FF FF | Reserved |
|
||||||
|
|
||||||
** Reserved Block 1
|
** Reserved Block 1
|
||||||
At this time these instructions only produce a warning; but could do anything.
|
At this time these instructions only produce a warning; but could do anything.
|
||||||
DO NOT USE.
|
DO NOT USE.
|
||||||
43 00 00 00 # Reserved
|
| Hex | Name |
|
||||||
...
|
|-------------+----------|
|
||||||
FE FF FF FF # Reserved
|
| 43 00 00 00 | Reserved |
|
||||||
|
| ... | Reserved |
|
||||||
|
| FE FF FF FF | Reserved |
|
||||||
|
|
||||||
** 0OP
|
** 0OP
|
||||||
FF xx xx xx # HALT equivelent, although these instructions will all be treated as HALTs. DO NOT USE THEM.
|
| Hex | Name | Comment |
|
||||||
FF FF FF FF # Proper HALT
|
|-------------+------------------+----------------------------------------------------------------------------|
|
||||||
|
| FF xx xx xx | HALT equivelent. | Although these instructions will all be treated as HALTs. DO NOT USE THEM. |
|
||||||
|
| FF FF FF FF | Proper HALT | |
|
||||||
|
|
||||||
* Encoding/Decoding Reference
|
* Encoding/Decoding Reference
|
||||||
** Registers
|
** Registers
|
||||||
There is a direct and consistent relationship between the nybbles and the registers.
|
There is a direct and consistent relationship between the nybbles and the registers.
|
||||||
Reg0 -> 0, Reg1 -> 1, ... Reg14 -> E, Reg15 -> F
|
| Hex | Name |
|
||||||
|
|-----+-------|
|
||||||
|
| 0 | REG0 |
|
||||||
|
| 1 | REG1 |
|
||||||
|
| 2 | REG2 |
|
||||||
|
| 3 | REG3 |
|
||||||
|
| 4 | REG4 |
|
||||||
|
| 5 | REG5 |
|
||||||
|
| 6 | REG6 |
|
||||||
|
| 7 | REG7 |
|
||||||
|
| 8 | REG8 |
|
||||||
|
| 9 | REG9 |
|
||||||
|
| A | REG10 |
|
||||||
|
| B | REG11 |
|
||||||
|
| C | REG12 |
|
||||||
|
| D | REG13 |
|
||||||
|
| E | REG14 |
|
||||||
|
| F | REG15 |
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue