Added indexed load/store instructions to vm, assembler and disassembler
This commit is contained in:
parent
67c0cda3d0
commit
e58abb8fb8
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@ -23,13 +23,13 @@
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01 0A ab cd # SUBU.BO a b c d :: a = b - c; d = BORROW? [unsigned]
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01 0A ab cd # SUBU.BO a b c d :: a = b - c; d = BORROW? [unsigned]
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01 0B ab cd # SUBU.BIO a b c d :: a = b - c - BORROW? d; d = BORROW? [unsigned]
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01 0B ab cd # SUBU.BIO a b c d :: a = b - c - BORROW? d; d = BORROW? [unsigned]
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**** long math
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**** long math subgroup
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01 0C ab cd # MULTIPLY a b c d :: a = MUL c d; b = MULH c d [signed]
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01 0C ab cd # MULTIPLY a b c d :: a = MUL c d; b = MULH c d [signed]
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01 0D ab cd # MULTIPLYU a b c d :: a = MUL c d; b = MULH c d [unsigned]
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01 0D ab cd # MULTIPLYU a b c d :: a = MUL c d; b = MULH c d [unsigned]
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01 0E ab cd # DIVIDE a b c d :: a = DIV c d; b = MOD c d [signed]
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01 0E ab cd # DIVIDE a b c d :: a = DIV c d; b = MOD c d [signed]
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01 0F ab cd # DIVIDEU a b c d :: a = DIV c d; b = MOD c d [unsigned]
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01 0F ab cd # DIVIDEU a b c d :: a = DIV c d; b = MOD c d [unsigned]
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**** Logic
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**** Logic subgroup
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01 10 ab cd # MUX a b c d :: a = (c & ~b) | (d & b)
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01 10 ab cd # MUX a b c d :: a = (c & ~b) | (d & b)
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01 11 ab cd # NMUX a b c d :: a = (c & b) | (d & ~b)
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01 11 ab cd # NMUX a b c d :: a = (c & b) | (d & ~b)
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01 12 ab cd # SORT a b c d :: a = MAX(c, d); b = MIN(c, d) [signed]
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01 12 ab cd # SORT a b c d :: a = MAX(c, d); b = MIN(c, d) [signed]
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@ -116,8 +116,36 @@
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05 03 6a bc # ROL a b c :: a = ROL(b, c) [Circular rotate left]
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05 03 6a bc # ROL a b c :: a = ROL(b, c) [Circular rotate left]
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05 03 7a bc # ROR a b c :: a = ROR(b, c) [Circular rotate right]
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05 03 7a bc # ROR a b c :: a = ROR(b, c) [Circular rotate right]
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**** Load group
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05 03 8a bc # LOADX a b c :: a = MEM[b+c]
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05 03 9a bc # LOADX8 a b c :: a = MEM[b+c] [signed 8bits]
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05 03 Aa bc # LOADXU8 a b c :: a = MEM[b+c] [unsigned 8bits]
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05 03 Ba bc # LOADX16 a b c :: a = MEM[b+c] [signed 16bits]
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05 03 Ca bc # LOADXU16 a b c :: a = MEM[b+c] [unsigned 16bits]
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05 03 Da bc # LOADX32 a b c :: a = MEM[b+c] [signed 32bits]
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05 03 Ea bc # LOADXU32 a b c :: a = MEM[b+c] [unsigned 32bits]
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05 03 Fx xx # Reserved
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05 04 0x xx # Reserved
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05 04 1x xx # Reserved
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05 04 2x xx # Reserved
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05 04 3x xx # Reserved
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05 04 4x xx # Reserved
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05 04 5x xx # Reserved
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05 04 6x xx # Reserved
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05 04 7x xx # Reserved
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**** Store group
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05 04 8a bc # STOREX a b c :: MEM[b+c] = a
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05 04 9a bc # STOREX8 a b c :: MEM[b+c] = a [8bits]
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05 04 Aa bc # STOREX16 a b c :: MEM[b+c] = a [16bits]
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05 04 Ba bc # STOREX32 a b c :: MEM[b+c] = a [32bits]
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05 04 Cx xx # Reserved
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05 04 Dx xx # Reserved
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05 04 Ex xx # Reserved
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05 04 Fx xx # Reserved
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**** Reserved group 2
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**** Reserved group 2
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05 03 8x xx # Reserved
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05 05 0x xx # Reserved
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...
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...
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05 FF Fx xx # Reserved
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05 FF Fx xx # Reserved
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@ -221,11 +249,11 @@
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*** 2OPI Integer store
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*** 2OPI Integer store
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20 ab ii ii # STORE a b ii :: MEM[b + ii ii] = a
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20 ab ii ii # STORE a b ii :: MEM[b + ii ii] = a
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21 ab ii ii # STORE8 a b ii :: MEM[b + ii ii] = a [signed 8bits]
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21 ab ii ii # STORE8 a b ii :: MEM[b + ii ii] = a [signed 8bits]
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22 ab ii ii # STOREU8 a b ii :: MEM[b + ii ii] = a [unsigned 8bits]
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22 ab ii ii # STORE16 a b ii :: MEM[b + ii ii] = a [signed 16bits]
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23 ab ii ii # STORE16 a b ii :: MEM[b + ii ii] = a [signed 16bits]
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23 ab ii ii # STORE32 a b ii :: MEM[b + ii ii] = a [signed 32bits]
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24 ab ii ii # STOREU16 a b ii :: MEM[b + ii ii] = a [unsigned 16bits]
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24 ab ii ii # Reserved
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25 ab ii ii # STORE32 a b ii :: MEM[b + ii ii] = a [signed 32bits]
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25 ab ii ii # Reserved
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26 ab ii ii # STOREU32 a b ii :: MEM[b + ii ii] = a [unsigned 32bits]
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26 ab ii ii # Reserved
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27 ab ii ii # Reserved
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27 ab ii ii # Reserved
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28 ab ii ii # Reserved
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28 ab ii ii # Reserved
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29 ab ii ii # Reserved
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29 ab ii ii # Reserved
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18
asm.c
18
asm.c
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@ -232,6 +232,17 @@ void assemble(struct Token* p)
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setExpression(p, "SR1", "05035", 4);
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setExpression(p, "SR1", "05035", 4);
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setExpression(p, "ROL", "05036", 4);
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setExpression(p, "ROL", "05036", 4);
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setExpression(p, "ROR", "05037", 4);
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setExpression(p, "ROR", "05037", 4);
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setExpression(p, "LOADX", "05038", 4);
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setExpression(p, "LOADX8", "05039", 4);
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setExpression(p, "LOADXU8", "0503A", 4);
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setExpression(p, "LOADX16", "0503B", 4);
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setExpression(p, "LOADXU16", "0503C", 4);
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setExpression(p, "LOADX32", "0503D", 4);
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setExpression(p, "LOADXU32", "0503E", 4);
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setExpression(p, "STOREX", "05048", 4);
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setExpression(p, "STOREX8", "05049", 4);
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setExpression(p, "STOREX16", "0504A", 4);
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setExpression(p, "STOREX32", "0504B", 4);
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/* 2OP Integer Group */
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/* 2OP Integer Group */
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setExpression(p, "NEG", "090000", 4);
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setExpression(p, "NEG", "090000", 4);
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@ -269,11 +280,8 @@ void assemble(struct Token* p)
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setExpression(p, "CMPUI", "1F", 4);
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setExpression(p, "CMPUI", "1F", 4);
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setExpression(p, "STORE", "20", 4);
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setExpression(p, "STORE", "20", 4);
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setExpression(p, "STORE8", "21", 4);
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setExpression(p, "STORE8", "21", 4);
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setExpression(p, "STOREU8", "22", 4);
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setExpression(p, "STORE16", "22", 4);
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setExpression(p, "STORE16", "23", 4);
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setExpression(p, "STORE32", "23", 4);
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setExpression(p, "STOREU16", "24", 4);
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setExpression(p, "STORE32", "25", 4);
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setExpression(p, "STOREU32", "26", 4);
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/* 1OPI Group */
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/* 1OPI Group */
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setExpression(p, "JUMP.C", "2C0", 4);
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setExpression(p, "JUMP.C", "2C0", 4);
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88
disasm.c
88
disasm.c
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@ -189,7 +189,7 @@ void decode_Integer_4OP(struct Instruction* c)
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break;
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break;
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o reg%o reg%o reg%o\t", Name, c->reg0, c->reg1, c->reg2, c->reg3);
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fprintf(stdout, "%s reg%u reg%u reg%u reg%u\t", Name, c->reg0, c->reg1, c->reg2, c->reg3);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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@ -430,13 +430,68 @@ void decode_Integer_3OP(struct Instruction* c)
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strncpy(Name, "ROR", 19);
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strncpy(Name, "ROR", 19);
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break;
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break;
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}
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}
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case 0x038: /* LOADX */
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{
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strncpy(Name, "LOADX", 19);
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break;
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}
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case 0x039: /* LOADX8 */
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{
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strncpy(Name, "LOADX8", 19);
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break;
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}
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case 0x03A: /* LOADXU8 */
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{
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strncpy(Name, "LOADXU8", 19);
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break;
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}
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case 0x03B: /* LOADX16 */
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{
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strncpy(Name, "LOADX16", 19);
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break;
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}
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case 0x03C: /* LOADXU16 */
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{
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strncpy(Name, "LOADXU16", 19);
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break;
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}
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case 0x03D: /* LOADX32 */
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{
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strncpy(Name, "LOADX32", 19);
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break;
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}
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case 0x03E: /* LOADXU32 */
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{
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strncpy(Name, "LOADXU32", 19);
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break;
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}
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case 0x048: /* STOREX */
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{
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strncpy(Name, "STOREX", 19);
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break;
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}
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case 0x049: /* STOREX8 */
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{
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strncpy(Name, "STOREX8", 19);
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break;
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}
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case 0x04A: /* STOREX16 */
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{
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strncpy(Name, "STOREX16", 19);
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break;
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}
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case 0x04B: /* STOREX32 */
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{
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strncpy(Name, "STOREX32", 19);
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break;
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}
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default: /* Unknown 3OP*/
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default: /* Unknown 3OP*/
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{
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{
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break;
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break;
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o reg%o reg%o\t", Name, c->reg0, c->reg1, c->reg2);
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fprintf(stdout, "%s reg%u reg%u reg%u\t", Name, c->reg0, c->reg1, c->reg2);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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@ -503,7 +558,7 @@ void decode_Integer_2OP(struct Instruction* c)
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o reg%o\t", Name, c->reg0, c->reg1);
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fprintf(stdout, "%s reg%u reg%u\t", Name, c->reg0, c->reg1);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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@ -570,7 +625,7 @@ void decode_1OP(struct Instruction* c)
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o\t", Name, c->reg0);
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fprintf(stdout, "%s reg%u\t", Name, c->reg0);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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@ -706,38 +761,23 @@ void decode_Integer_2OPI(struct Instruction* c)
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strncpy(Name, "STORE8", 19);
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strncpy(Name, "STORE8", 19);
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break;
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break;
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}
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}
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case 0x22: /* STOREU8 */
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case 0x22: /* STORE16 */
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{
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strncpy(Name, "STOREU8", 19);
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break;
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}
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case 0x23: /* STORE16 */
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{
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{
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strncpy(Name, "STORE16", 19);
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strncpy(Name, "STORE16", 19);
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break;
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break;
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}
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}
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case 0x24: /* STOREU16 */
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case 0x23: /* STORE32 */
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{
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strncpy(Name, "STOREU16", 19);
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break;
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}
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case 0x25: /* STORE32 */
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{
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{
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strncpy(Name, "STORE32", 19);
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strncpy(Name, "STORE32", 19);
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break;
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break;
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}
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}
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case 0x26: /* STOREU32 */
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{
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strncpy(Name, "STOREU32", 19);
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break;
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}
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default: /* Unknown 2OPI*/
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default: /* Unknown 2OPI*/
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{
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{
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break;
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break;
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o reg%o 0x%x\t", Name, c->reg0, c->reg1, c->raw_Immediate);
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fprintf(stdout, "%s reg%u reg%u 0x%x\t", Name, c->reg0, c->reg1, c->raw_Immediate);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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@ -820,7 +860,7 @@ void decode_1OPI(struct Instruction* c)
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o %d\t", Name, c->reg0, c->raw_Immediate);
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fprintf(stdout, "%s reg%u %d\t", Name, c->reg0, c->raw_Immediate);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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@ -893,7 +933,7 @@ void decode_Branch_1OPI(struct Instruction* c)
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}
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}
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}
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}
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fprintf(stdout, "%s reg%o %d\t", Name, c->reg0, c->raw_Immediate);
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fprintf(stdout, "%s reg%u %d\t", Name, c->reg0, c->raw_Immediate);
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fprintf(stdout, "# %s\n", c->operation);
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fprintf(stdout, "# %s\n", c->operation);
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}
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}
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59
vm.h
59
vm.h
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@ -200,7 +200,8 @@ void writeout_Reg(struct lilith* vm, uint32_t p, uint32_t value)
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/* Allow the use of native data format for Register operations */
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/* Allow the use of native data format for Register operations */
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uint32_t readin_Reg(struct lilith* vm, uint32_t p)
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uint32_t readin_Reg(struct lilith* vm, uint32_t p)
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{
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{
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uint8_t raw0, raw1, raw2, raw3, sum;
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uint8_t raw0, raw1, raw2, raw3;
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uint32_t sum;
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raw0 = vm->memory[p];
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raw0 = vm->memory[p];
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raw1 = vm->memory[p + 1];
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raw1 = vm->memory[p + 1];
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raw2 = vm->memory[p + 2];
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raw2 = vm->memory[p + 2];
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return sum;
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return sum;
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}
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}
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/* Unify byte write functionality */
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void writeout_byte(struct lilith* vm, uint32_t p, uint32_t value)
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{
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vm->memory[p] = (uint8_t)(value%0x100);
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}
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/* Unify byte read functionality*/
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uint32_t readin_byte(struct lilith* vm, uint32_t p, bool Signed)
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{
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if(Signed)
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{
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int32_t raw0;
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raw0 = (int8_t)(vm->memory[p]);
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return (uint32_t)(raw0);
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}
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return (uint32_t)(vm->memory[p]);
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}
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/* Unify doublebyte write functionality */
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void writeout_doublebyte(struct lilith* vm, uint32_t p, uint32_t value)
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{
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uint8_t uraw0, uraw1;
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uint32_t utmp = value;
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utmp = utmp/0x10000;
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uraw1 = utmp%0x100;
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utmp = utmp/0x100;
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uraw0 = utmp%0x100;
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vm->memory[p] = uraw0;
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vm->memory[p + 1] = uraw1;
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}
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/* Unify doublebyte read functionality*/
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uint32_t readin_doublebyte(struct lilith* vm, uint32_t p, bool Signed)
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{
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if(Signed)
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{
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int8_t raw0, raw1;
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||||||
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int32_t sum;
|
||||||
|
raw0 = vm->memory[p];
|
||||||
|
raw1 = vm->memory[p + 1];
|
||||||
|
|
||||||
|
sum = raw0*0x100 + raw1;
|
||||||
|
return (uint32_t)(sum);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t uraw0, uraw1;
|
||||||
|
uint32_t usum;
|
||||||
|
uraw0 = vm->memory[p];
|
||||||
|
uraw1 = vm->memory[p + 1];
|
||||||
|
|
||||||
|
usum = uraw0*0x100 + uraw1;
|
||||||
|
return usum;
|
||||||
|
}
|
||||||
|
|
||||||
/* Determine the result of bit shifting */
|
/* Determine the result of bit shifting */
|
||||||
uint32_t shift_register(uint32_t source, uint32_t amount, bool left, bool zero)
|
uint32_t shift_register(uint32_t source, uint32_t amount, bool left, bool zero)
|
||||||
{
|
{
|
||||||
|
|
Loading…
Reference in New Issue