2014-02-01 07:51:28 +00:00
|
|
|
/*
|
2018-10-31 15:25:35 +00:00
|
|
|
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
2014-02-01 07:51:28 +00:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2014-02-01 07:51:28 +00:00
|
|
|
*/
|
|
|
|
|
2018-10-31 15:25:35 +00:00
|
|
|
#ifndef CONTEXT_MGMT_H
|
|
|
|
#define CONTEXT_MGMT_H
|
2014-02-01 07:51:28 +00:00
|
|
|
|
Introduce ARM SiP service to switch execution state
In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether the lower exception level executes in AArch64 or AArch32 state.
For an exception level to have its execution state changed at run time,
it must request the change by raising a synchronous exception to the
higher exception level.
This patch implements and adds such a provision to the ARM SiP service,
by which an immediate lower exception level can request to switch its
execution state. The execution state is switched if the request is:
- raised from non-secure world;
- raised on the primary CPU, before any secondaries are brought online
with CPU_ON PSCI call;
- raised from an exception level immediately below EL3: EL2, if
implemented; otherwise NS EL1.
If successful, the SMC doesn't return to the caller, but to the entry
point supplied with the call. Otherwise, the caller will observe the SMC
returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built
for AArch32, the feature is not supported, and the call will always
fail.
For the ARM SiP service:
- Add SMC function IDs for both AArch32 and AArch64;
- Increment the SiP service minor version to 2;
- Adjust the number of supported SiP service calls.
Add documentation for ARM SiP service.
Fixes ARM-software/tf-issues#436
Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-02-16 14:55:15 +00:00
|
|
|
#include <assert.h>
|
2018-05-22 10:09:10 +01:00
|
|
|
#include <context.h>
|
Introduce ARM SiP service to switch execution state
In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether the lower exception level executes in AArch64 or AArch32 state.
For an exception level to have its execution state changed at run time,
it must request the change by raising a synchronous exception to the
higher exception level.
This patch implements and adds such a provision to the ARM SiP service,
by which an immediate lower exception level can request to switch its
execution state. The execution state is switched if the request is:
- raised from non-secure world;
- raised on the primary CPU, before any secondaries are brought online
with CPU_ON PSCI call;
- raised from an exception level immediately below EL3: EL2, if
implemented; otherwise NS EL1.
If successful, the SMC doesn't return to the caller, but to the entry
point supplied with the call. Otherwise, the caller will observe the SMC
returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built
for AArch32, the feature is not supported, and the call will always
fail.
For the ARM SiP service:
- Add SMC function IDs for both AArch32 and AArch64;
- Increment the SiP service minor version to 2;
- Adjust the number of supported SiP service calls.
Add documentation for ARM SiP service.
Fixes ARM-software/tf-issues#436
Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-02-16 14:55:15 +00:00
|
|
|
#include <stdint.h>
|
2014-02-01 07:51:28 +00:00
|
|
|
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <arch.h>
|
|
|
|
|
2014-06-04 21:10:52 +01:00
|
|
|
/*******************************************************************************
|
|
|
|
* Forward declarations
|
|
|
|
******************************************************************************/
|
|
|
|
struct entry_point_info;
|
|
|
|
|
2014-02-01 07:51:28 +00:00
|
|
|
/*******************************************************************************
|
|
|
|
* Function & variable prototypes
|
|
|
|
******************************************************************************/
|
2014-05-14 12:38:32 +01:00
|
|
|
void cm_init(void);
|
2015-04-09 13:40:55 +01:00
|
|
|
void *cm_get_context_by_index(unsigned int cpu_idx,
|
|
|
|
unsigned int security_state);
|
|
|
|
void cm_set_context_by_index(unsigned int cpu_idx,
|
|
|
|
void *context,
|
|
|
|
unsigned int security_state);
|
2015-10-02 17:56:48 +01:00
|
|
|
void *cm_get_context(uint32_t security_state);
|
|
|
|
void cm_set_context(void *context, uint32_t security_state);
|
2015-04-09 13:40:55 +01:00
|
|
|
void cm_init_my_context(const struct entry_point_info *ep);
|
|
|
|
void cm_init_context_by_index(unsigned int cpu_idx,
|
|
|
|
const struct entry_point_info *ep);
|
2018-05-22 10:09:10 +01:00
|
|
|
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep);
|
2014-06-04 21:10:52 +01:00
|
|
|
void cm_prepare_el3_exit(uint32_t security_state);
|
2016-05-05 14:10:46 +01:00
|
|
|
|
|
|
|
#ifndef AARCH32
|
2014-05-14 12:38:32 +01:00
|
|
|
void cm_el1_sysregs_context_save(uint32_t security_state);
|
|
|
|
void cm_el1_sysregs_context_restore(uint32_t security_state);
|
2016-06-16 14:52:04 +01:00
|
|
|
void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
|
2014-06-04 21:10:52 +01:00
|
|
|
void cm_set_elr_spsr_el3(uint32_t security_state,
|
2016-06-16 14:52:04 +01:00
|
|
|
uintptr_t entrypoint, uint32_t spsr);
|
2014-05-14 12:38:32 +01:00
|
|
|
void cm_write_scr_el3_bit(uint32_t security_state,
|
|
|
|
uint32_t bit_pos,
|
|
|
|
uint32_t value);
|
|
|
|
void cm_set_next_eret_context(uint32_t security_state);
|
|
|
|
uint32_t cm_get_scr_el3(uint32_t security_state);
|
2014-06-02 11:40:35 +01:00
|
|
|
|
2014-06-02 10:00:25 +01:00
|
|
|
/* Inline definitions */
|
|
|
|
|
|
|
|
/*******************************************************************************
|
2015-10-02 17:56:48 +01:00
|
|
|
* This function is used to program the context that's used for exception
|
|
|
|
* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
|
|
|
|
* the required security state
|
2014-06-02 10:00:25 +01:00
|
|
|
******************************************************************************/
|
2016-04-11 13:17:50 +01:00
|
|
|
static inline void cm_set_next_context(void *context)
|
2014-06-02 10:00:25 +01:00
|
|
|
{
|
2017-03-22 15:48:51 +00:00
|
|
|
#if ENABLE_ASSERTIONS
|
2015-10-02 17:56:48 +01:00
|
|
|
uint64_t sp_mode;
|
2014-06-02 10:00:25 +01:00
|
|
|
|
2015-10-02 17:56:48 +01:00
|
|
|
/*
|
|
|
|
* Check that this function is called with SP_EL0 as the stack
|
|
|
|
* pointer
|
|
|
|
*/
|
|
|
|
__asm__ volatile("mrs %0, SPSel\n"
|
|
|
|
: "=r" (sp_mode));
|
2014-06-02 10:00:25 +01:00
|
|
|
|
2015-10-02 17:56:48 +01:00
|
|
|
assert(sp_mode == MODE_SP_EL0);
|
2017-03-22 15:48:51 +00:00
|
|
|
#endif /* ENABLE_ASSERTIONS */
|
2014-06-02 10:00:25 +01:00
|
|
|
|
2015-10-02 17:56:48 +01:00
|
|
|
__asm__ volatile("msr spsel, #1\n"
|
|
|
|
"mov sp, %0\n"
|
|
|
|
"msr spsel, #0\n"
|
|
|
|
: : "r" (context));
|
2014-06-02 10:00:25 +01:00
|
|
|
}
|
2016-06-28 17:07:09 +01:00
|
|
|
|
|
|
|
#else
|
|
|
|
void *cm_get_next_context(void);
|
2017-06-23 08:37:49 +01:00
|
|
|
void cm_set_next_context(void *context);
|
2016-05-05 14:10:46 +01:00
|
|
|
#endif /* AARCH32 */
|
2016-06-28 17:07:09 +01:00
|
|
|
|
2018-10-31 15:25:35 +00:00
|
|
|
#endif /* CONTEXT_MGMT_H */
|