2016-11-10 16:17:51 +00:00
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/*
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2019-02-11 13:34:54 +00:00
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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2016-11-10 16:17:51 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2016-11-10 16:17:51 +00:00
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef CORTEX_A53_H
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#define CORTEX_A53_H
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:54 +00:00
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#include <lib/utils_def.h>
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2016-11-10 16:17:51 +00:00
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/* Cortex-A53 midr for revision 0 */
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A53_MIDR U(0x410FD030)
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2016-11-10 16:17:51 +00:00
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/* Retention timer tick definitions */
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2019-02-11 13:34:15 +00:00
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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2016-11-10 16:17:51 +00:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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2017-06-05 22:54:46 +01:00
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#define CORTEX_A53_ECTLR p15, 1, c15
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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2016-11-10 16:17:51 +00:00
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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2017-06-05 22:54:46 +01:00
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#define CORTEX_A53_MERRSR p15, 2, c15
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2016-11-10 16:17:51 +00:00
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_CPUACTLR p15, 0, c15
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:54 +00:00
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#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24)
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#define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT)
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2016-11-10 16:17:51 +00:00
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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2017-06-05 22:54:46 +01:00
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#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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2016-11-10 16:17:51 +00:00
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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2017-06-05 22:54:46 +01:00
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#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
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2016-11-10 16:17:51 +00:00
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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2016-11-10 16:17:51 +00:00
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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2017-06-05 22:54:46 +01:00
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#define CORTEX_A53_L2MERRSR p15, 3, c15
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2016-11-10 16:17:51 +00:00
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2018-11-08 10:20:19 +00:00
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#endif /* CORTEX_A53_H */
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