2013-10-25 09:08:21 +01:00
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/*
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2016-06-16 14:52:04 +01:00
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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2013-10-25 09:08:21 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2013-10-25 09:08:21 +01:00
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*/
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#include <bakery_lock.h>
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2014-04-09 13:14:54 +01:00
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#include <mmio.h>
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2015-03-19 19:17:53 +00:00
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#include <plat_arm.h>
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2014-05-14 17:44:19 +01:00
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#include "../../fvp_def.h"
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2015-01-08 18:02:19 +00:00
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#include "../../fvp_private.h"
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2014-04-11 11:52:12 +01:00
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#include "fvp_pwrc.h"
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2013-10-25 09:08:21 +01:00
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/*
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* TODO: Someday there will be a generic power controller api. At the moment
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* each platform has its own pwrc so just exporting functions is fine.
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*/
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2015-03-19 19:17:53 +00:00
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ARM_INSTANTIATE_LOCK
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2013-10-25 09:08:21 +01:00
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2016-06-16 14:52:04 +01:00
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unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
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2013-10-25 09:08:21 +01:00
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{
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2014-06-09 12:54:15 +01:00
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return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
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2013-10-25 09:08:21 +01:00
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}
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2016-06-16 14:52:04 +01:00
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unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
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2013-10-25 09:08:21 +01:00
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{
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2014-06-09 12:54:15 +01:00
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unsigned int rc;
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2015-03-19 19:17:53 +00:00
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arm_lock_get();
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2013-10-25 09:08:21 +01:00
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mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
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rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
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2015-03-19 19:17:53 +00:00
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arm_lock_release();
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2013-10-25 09:08:21 +01:00
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return rc;
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}
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2016-06-16 14:52:04 +01:00
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void fvp_pwrc_write_pponr(u_register_t mpidr)
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2013-10-25 09:08:21 +01:00
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{
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2015-03-19 19:17:53 +00:00
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arm_lock_get();
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2013-10-25 09:08:21 +01:00
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mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
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2015-03-19 19:17:53 +00:00
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arm_lock_release();
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2013-10-25 09:08:21 +01:00
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}
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2016-06-16 14:52:04 +01:00
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void fvp_pwrc_write_ppoffr(u_register_t mpidr)
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2013-10-25 09:08:21 +01:00
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{
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2015-03-19 19:17:53 +00:00
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arm_lock_get();
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2013-10-25 09:08:21 +01:00
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mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
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2015-03-19 19:17:53 +00:00
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arm_lock_release();
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2013-10-25 09:08:21 +01:00
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}
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2016-06-16 14:52:04 +01:00
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void fvp_pwrc_set_wen(u_register_t mpidr)
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2013-10-25 09:08:21 +01:00
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{
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2015-03-19 19:17:53 +00:00
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arm_lock_get();
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2013-10-25 09:08:21 +01:00
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mmio_write_32(PWRC_BASE + PWKUPR_OFF,
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(unsigned int) (PWKUPR_WEN | mpidr));
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2015-03-19 19:17:53 +00:00
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arm_lock_release();
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2013-10-25 09:08:21 +01:00
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}
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2016-06-16 14:52:04 +01:00
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void fvp_pwrc_clr_wen(u_register_t mpidr)
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2013-11-12 16:40:00 +00:00
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{
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2015-03-19 19:17:53 +00:00
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arm_lock_get();
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2013-11-12 16:40:00 +00:00
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mmio_write_32(PWRC_BASE + PWKUPR_OFF,
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(unsigned int) mpidr);
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2015-03-19 19:17:53 +00:00
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arm_lock_release();
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2013-11-12 16:40:00 +00:00
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}
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2016-06-16 14:52:04 +01:00
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void fvp_pwrc_write_pcoffr(u_register_t mpidr)
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2013-10-25 09:08:21 +01:00
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{
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2015-03-19 19:17:53 +00:00
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arm_lock_get();
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2013-10-25 09:08:21 +01:00
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mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
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2015-03-19 19:17:53 +00:00
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arm_lock_release();
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2013-10-25 09:08:21 +01:00
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}
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/* Nothing else to do here apart from initializing the lock */
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2015-03-19 19:17:53 +00:00
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void plat_arm_pwrc_setup(void)
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2013-10-25 09:08:21 +01:00
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{
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2015-03-19 19:17:53 +00:00
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arm_lock_init();
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2013-10-25 09:08:21 +01:00
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}
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