2015-03-19 18:58:55 +00:00
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/*
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2018-01-05 16:00:05 +00:00
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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2015-03-19 18:58:55 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2015-03-19 18:58:55 +00:00
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*/
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2019-01-15 14:19:50 +00:00
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#include <platform_def.h>
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2019-01-25 14:30:04 +00:00
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#include <plat/arm/common/plat_arm.h>
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2015-03-19 18:58:55 +00:00
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/*
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2016-05-18 16:11:47 +01:00
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* Table of memory regions for different BL stages to map using the MMU.
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2018-10-19 16:44:18 +01:00
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* This doesn't include Trusted SRAM as setup_page_tables() already takes care
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* of mapping it.
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2015-03-19 18:58:55 +00:00
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*/
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2016-12-25 14:36:24 +00:00
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#ifdef IMAGE_BL1
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2015-03-19 18:58:55 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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2018-03-07 11:32:04 +00:00
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V2M_MAP_FLASH0_RW,
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2015-03-19 18:58:55 +00:00
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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2015-10-11 14:14:55 +01:00
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#if TRUSTED_BOARD_BOOT
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2017-05-26 15:48:10 +01:00
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/* Map DRAM to authenticate NS_BL2U image. */
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2015-10-11 14:14:55 +01:00
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ARM_MAP_NS_DRAM1,
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#endif
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2015-03-19 18:58:55 +00:00
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{0}
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};
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#endif
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2016-12-25 14:36:24 +00:00
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#ifdef IMAGE_BL2
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2015-03-19 18:58:55 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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2018-03-07 11:32:04 +00:00
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V2M_MAP_FLASH0_RW,
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2017-08-03 09:16:43 +01:00
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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2015-03-19 18:58:55 +00:00
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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ARM_MAP_NS_DRAM1,
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2017-08-08 11:27:20 +01:00
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#ifdef AARCH64
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ARM_MAP_DRAM2,
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#endif
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2017-08-30 10:59:22 +01:00
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#ifdef SPD_tspd
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2015-03-19 18:58:55 +00:00
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ARM_MAP_TSP_SEC_MEM,
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2017-08-30 10:59:22 +01:00
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#endif
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2017-04-24 16:49:28 +01:00
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#ifdef SPD_opteed
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2017-09-01 13:43:50 +01:00
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ARM_MAP_OPTEE_CORE_MEM,
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2017-04-24 16:49:28 +01:00
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ARM_OPTEE_PAGEABLE_LOAD_MEM,
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#endif
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2015-03-19 18:58:55 +00:00
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{0}
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};
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#endif
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2016-12-25 14:36:24 +00:00
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#ifdef IMAGE_BL2U
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2015-10-14 15:28:11 +01:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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CSS_MAP_DEVICE,
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2018-07-06 16:54:44 +01:00
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CSS_MAP_SCP_BL2U,
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V2M_MAP_IOFPGA,
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2015-10-14 15:28:11 +01:00
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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#endif
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2016-12-25 14:36:24 +00:00
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#ifdef IMAGE_BL31
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2015-03-19 18:58:55 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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2017-08-03 09:16:43 +01:00
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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2015-03-19 18:58:55 +00:00
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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#endif
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2016-12-25 14:36:24 +00:00
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#ifdef IMAGE_BL32
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2015-03-19 18:58:55 +00:00
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const mmap_region_t plat_arm_mmap[] = {
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2016-11-14 12:00:41 +00:00
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#ifdef AARCH32
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ARM_MAP_SHARED_RAM,
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2018-01-05 16:00:05 +00:00
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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2016-11-14 12:00:41 +00:00
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#endif
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2015-03-19 18:58:55 +00:00
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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#endif
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ARM_CASSERT_MMAP
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