60 lines
1.6 KiB
Makefile
60 lines
1.6 KiB
Makefile
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#
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# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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RESET_TO_BL31 := 1
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ifeq (${RESET_TO_BL31}, 0)
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$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
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endif
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CTX_INCLUDE_AARCH32_REGS := 0
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ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
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$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
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endif
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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$(error "TRUSTED_BOARD_BOOT must be disabled")
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endif
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ifndef PRELOADED_BL33_BASE
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$(error "PRELOADED_BL33_BASE is not set")
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endif
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ifndef FPGA_PRELOADED_DTB_BASE
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$(error "FPGA_PRELOADED_DTB_BASE is not set")
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else
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$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
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endif
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# Treating this as a memory-constrained port for now
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USE_COHERENT_MEM := 0
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# The CPU in the initial image makes use of this feature
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HW_ASSISTED_COHERENCY := 1
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FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S \
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lib/cpus/aarch64/neoverse_zeus.S
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FPGA_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v3/gicv3_main.c \
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plat/common/plat_gicv3.c
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PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
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BL31_SOURCES += drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/arm/pl011/${ARCH}/pl011_console.S \
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plat/common/plat_psci_common.c \
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plat/arm/board/arm_fpga/fpga_pm.c \
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plat/arm/board/arm_fpga/fpga_topology.c \
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plat/arm/board/arm_fpga/fpga_console.c \
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plat/arm/board/arm_fpga/fpga_bl31_setup.c \
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${FPGA_CPU_LIBS} \
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${FPGA_GIC_SOURCES}
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all: bl31
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