arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_private.h

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/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __XLAT_TABLES_PRIVATE_H__
#define __XLAT_TABLES_PRIVATE_H__
#include <platform_def.h>
xlat lib: Reorganize architectural defs Move the header files that provide translation tables architectural definitions from the library v2 source files to the library include directory. This allows to share these definitions between both versions (v1 and v2) of the library. Create a new header file that includes the AArch32 or AArch64 definitions based on the AARCH32 build flag, so that the library user doesn't have to worry about handling it on their side. Also repurpose some of the definitions the header files provide to concentrate on the things that differ between AArch32 and AArch64. As a result they now contain the following information: - the first table level that allows block descriptors; - the architectural limits of the virtual address space; - the initial lookup level to cover the entire address space. Additionally, move the XLAT_TABLE_LEVEL_MIN macro from xlat_tables_defs.h to the AArch32/AArch64 architectural definitions. This new organisation eliminates duplicated information in the AArch32 and AArch64 versions. It also decouples these architectural files from any platform-specific information. Previously, they were dependent on the address space size, which is platform-specific. Finally, for the v2 of the library, move the compatibility code for ADDR_SPACE_SIZE into a C file as it is not needed outside of this file. For v1, this code hasn't been changed and stays in a header file because it's needed by several files. Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-05-19 09:59:37 +01:00
#include <xlat_tables_defs.h>
#if PLAT_XLAT_TABLES_DYNAMIC
/*
* Shifts and masks to access fields of an mmap_attr_t
*/
/* Dynamic or static */
#define MT_DYN_SHIFT 30 /* 31 would cause undefined behaviours */
/*
* Memory mapping private attributes
*
* Private attributes not exposed in the mmap_attr_t enum.
*/
typedef enum {
/*
* Regions mapped before the MMU can't be unmapped dynamically (they are
* static) and regions mapped with MMU enabled can be unmapped. This
* behaviour can't be overridden.
*
* Static regions can overlap each other, dynamic regions can't.
*/
MT_STATIC = 0 << MT_DYN_SHIFT,
MT_DYNAMIC = 1 << MT_DYN_SHIFT
} mmap_priv_attr_t;
#endif /* PLAT_XLAT_TABLES_DYNAMIC */
/*
* Invalidate all TLB entries that match the given virtual address. This
* operation applies to all PEs in the same Inner Shareable domain as the PE
* that executes this function. This functions must be called for every
* translation table entry that is modified.
*
* xlat_arch_tlbi_va() applies the invalidation to the exception level of the
* current translation regime, whereas xlat_arch_tlbi_va_regime() applies it to
* the given translation regime.
*
* Note, however, that it is architecturally UNDEFINED to invalidate TLB entries
* pertaining to a higher exception level, e.g. invalidating EL3 entries from
* S-EL1.
*/
void xlat_arch_tlbi_va(uintptr_t va);
void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime);
/*
* This function has to be called at the end of any code that uses the function
* xlat_arch_tlbi_va().
*/
void xlat_arch_tlbi_va_sync(void);
/* Print VA, PA, size and attributes of all regions in the mmap array. */
void print_mmap(mmap_region_t *const mmap);
/*
* Print the current state of the translation tables by reading them from
* memory.
*/
void xlat_tables_print(xlat_ctx_t *ctx);
/*
* Architecture-specific initialization code.
*/
Fix execute-never permissions in xlat tables libs Translation regimes that only support one virtual address space (such as the ones for EL2 and EL3) can flag memory regions as execute-never by setting to 1 the XN bit in the Upper Attributes field in the translation tables descriptors. Translation regimes that support two different virtual address spaces (such as the one shared by EL1 and EL0) use bits PXN and UXN instead. The Trusted Firmware runs at EL3 and EL1, it has to handle translation tables of both translation regimes, but the previous code handled both regimes the same way, as if both had only 1 VA range. When trying to set a descriptor as execute-never it would set the XN bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is at the same bit position as UXN, which means that EL0 was being prevented from executing code at this region, not EL1 as the code intended. Therefore, the PXN bit was unset to 0 all the time. The result is that, in AArch64 mode, read-only data sections of BL2 weren't protected from being executed. This patch adds support of translation regimes with two virtual address spaces to both versions of the translation tables library, fixing the execute-never permissions for translation tables in EL1. The library currently does not support initializing translation tables for EL0 software, therefore it does not set/unset the UXN bit. If EL1 software needs to initialize translation tables for EL0 software, it should use a different library instead. Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-27 13:30:22 +01:00
/* Returns the current Exception Level. The returned EL must be 1 or higher. */
int xlat_arch_current_el(void);
/*
* Return the maximum physical address supported by the hardware.
* This value depends on the execution state (AArch32/AArch64).
*/
unsigned long long xlat_arch_get_max_supported_pa(void);
/* Enable MMU and configure it to use the specified translation tables. */
void enable_mmu_arch(unsigned int flags, uint64_t *base_table,
unsigned long long max_pa, uintptr_t max_va);
/*
* Return 1 if the MMU of the translation regime managed by the given xlat_ctx_t
* is enabled, 0 otherwise.
*/
int is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
#endif /* __XLAT_TABLES_PRIVATE_H__ */