2015-11-03 14:18:34 +00:00
|
|
|
/*
|
2019-01-11 18:26:51 +00:00
|
|
|
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
2015-11-03 14:18:34 +00:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2015-11-03 14:18:34 +00:00
|
|
|
*/
|
|
|
|
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <platform_def.h>
|
|
|
|
|
|
|
|
#include <common/interrupt_props.h>
|
|
|
|
#include <drivers/arm/gicv3.h>
|
|
|
|
#include <lib/utils.h>
|
2019-01-25 14:30:04 +00:00
|
|
|
#include <plat/arm/common/plat_arm.h>
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <plat/common/platform.h>
|
|
|
|
|
2015-11-03 14:18:34 +00:00
|
|
|
/******************************************************************************
|
|
|
|
* The following functions are defined as weak to allow a platform to override
|
|
|
|
* the way the GICv3 driver is initialised and used.
|
|
|
|
*****************************************************************************/
|
|
|
|
#pragma weak plat_arm_gic_driver_init
|
|
|
|
#pragma weak plat_arm_gic_init
|
|
|
|
#pragma weak plat_arm_gic_cpuif_enable
|
|
|
|
#pragma weak plat_arm_gic_cpuif_disable
|
|
|
|
#pragma weak plat_arm_gic_pcpu_init
|
2016-12-09 11:12:34 +00:00
|
|
|
#pragma weak plat_arm_gic_redistif_on
|
|
|
|
#pragma weak plat_arm_gic_redistif_off
|
2015-11-03 14:18:34 +00:00
|
|
|
|
|
|
|
/* The GICv3 driver only needs to be initialized in EL3 */
|
2016-01-13 17:06:00 +00:00
|
|
|
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
2015-11-03 14:18:34 +00:00
|
|
|
|
2017-09-22 08:59:59 +01:00
|
|
|
static const interrupt_prop_t arm_interrupt_props[] = {
|
|
|
|
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
|
|
|
|
PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
|
2015-11-03 14:18:34 +00:00
|
|
|
};
|
|
|
|
|
2017-10-11 16:08:58 +01:00
|
|
|
/*
|
|
|
|
* We save and restore the GICv3 context on system suspend. Allocate the
|
2018-10-12 16:26:20 +01:00
|
|
|
* data in the designated EL3 Secure carve-out memory. The `volatile`
|
|
|
|
* is used to prevent the compiler from removing the gicv3 contexts even
|
|
|
|
* though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it.
|
2017-10-11 16:08:58 +01:00
|
|
|
*/
|
2018-10-12 16:26:20 +01:00
|
|
|
static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
|
|
|
|
static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
|
|
|
|
|
|
|
|
/* Define accessor function to get reference to the GICv3 context */
|
|
|
|
DEFINE_LOAD_SYM_ADDR(rdist_ctx)
|
|
|
|
DEFINE_LOAD_SYM_ADDR(dist_ctx)
|
2017-10-11 16:08:58 +01:00
|
|
|
|
2016-11-15 13:53:57 +00:00
|
|
|
/*
|
|
|
|
* MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
|
|
|
|
* to core position.
|
|
|
|
*
|
|
|
|
* Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
|
|
|
|
* values read from GICR_TYPER don't have an MT field. To reuse the same
|
|
|
|
* translation used for CPUs, we insert MT bit read from the PE's MPIDR into
|
|
|
|
* that read from GICR_TYPER.
|
|
|
|
*
|
|
|
|
* Assumptions:
|
|
|
|
*
|
|
|
|
* - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
|
|
|
|
* - No CPUs implemented in the system use affinity level 3.
|
|
|
|
*/
|
|
|
|
static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
|
|
|
|
{
|
|
|
|
mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
|
|
|
|
return plat_arm_calc_core_pos(mpidr);
|
|
|
|
}
|
|
|
|
|
2018-02-12 12:36:17 +00:00
|
|
|
static const gicv3_driver_data_t arm_gic_data __unused = {
|
2015-11-03 14:18:34 +00:00
|
|
|
.gicd_base = PLAT_ARM_GICD_BASE,
|
|
|
|
.gicr_base = PLAT_ARM_GICR_BASE,
|
2017-09-22 08:59:59 +01:00
|
|
|
.interrupt_props = arm_interrupt_props,
|
|
|
|
.interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
|
2015-11-03 14:18:34 +00:00
|
|
|
.rdistif_num = PLATFORM_CORE_COUNT,
|
|
|
|
.rdistif_base_addrs = rdistif_base_addrs,
|
2016-11-15 13:53:57 +00:00
|
|
|
.mpidr_to_core_pos = arm_gicv3_mpidr_hash
|
2015-11-03 14:18:34 +00:00
|
|
|
};
|
|
|
|
|
2018-09-18 13:36:39 +01:00
|
|
|
void __init plat_arm_gic_driver_init(void)
|
2015-11-03 14:18:34 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The GICv3 driver is initialized in EL3 and does not need
|
|
|
|
* to be initialized again in SEL1. This is because the S-EL1
|
|
|
|
* can use GIC system registers to manage interrupts and does
|
|
|
|
* not need GIC interface base addresses to be configured.
|
|
|
|
*/
|
Use #ifdef for AARCH32 instead of #if
One nasty part of ATF is some of boolean macros are always defined
as 1 or 0, and the rest of them are only defined under certain
conditions.
For the former group, "#if FOO" or "#if !FOO" must be used because
"#ifdef FOO" is always true. (Options passed by $(call add_define,)
are the cases.)
For the latter, "#ifdef FOO" or "#ifndef FOO" should be used because
checking the value of an undefined macro is strange.
For AARCH32/AARCH64, these macros are defined in the top-level
Makefile as follows:
ifeq (${ARCH},aarch32)
$(eval $(call add_define,AARCH32))
else
$(eval $(call add_define,AARCH64))
endif
This means only one of the two is defined. So, AARCH32/AARCH64
belongs to the latter group where we should use #ifdef or #ifndef.
The conditionals are mostly coded correctly, but I see some mistakes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-25 15:22:47 +00:00
|
|
|
#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
|
|
|
|
(defined(IMAGE_BL31) && !defined(AARCH32))
|
2015-11-03 14:18:34 +00:00
|
|
|
gicv3_driver_init(&arm_gic_data);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* ARM common helper to initialize the GIC. Only invoked by BL31
|
|
|
|
*****************************************************************************/
|
2018-09-18 13:36:39 +01:00
|
|
|
void __init plat_arm_gic_init(void)
|
2015-11-03 14:18:34 +00:00
|
|
|
{
|
|
|
|
gicv3_distif_init();
|
|
|
|
gicv3_rdistif_init(plat_my_core_pos());
|
|
|
|
gicv3_cpuif_enable(plat_my_core_pos());
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* ARM common helper to enable the GIC CPU interface
|
|
|
|
*****************************************************************************/
|
|
|
|
void plat_arm_gic_cpuif_enable(void)
|
|
|
|
{
|
|
|
|
gicv3_cpuif_enable(plat_my_core_pos());
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* ARM common helper to disable the GIC CPU interface
|
|
|
|
*****************************************************************************/
|
|
|
|
void plat_arm_gic_cpuif_disable(void)
|
|
|
|
{
|
|
|
|
gicv3_cpuif_disable(plat_my_core_pos());
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* ARM common helper to initialize the per-cpu redistributor interface in GICv3
|
|
|
|
*****************************************************************************/
|
|
|
|
void plat_arm_gic_pcpu_init(void)
|
|
|
|
{
|
|
|
|
gicv3_rdistif_init(plat_my_core_pos());
|
|
|
|
}
|
2016-12-09 11:12:34 +00:00
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* ARM common helpers to power GIC redistributor interface
|
|
|
|
*****************************************************************************/
|
|
|
|
void plat_arm_gic_redistif_on(void)
|
|
|
|
{
|
|
|
|
gicv3_rdistif_on(plat_my_core_pos());
|
|
|
|
}
|
|
|
|
|
|
|
|
void plat_arm_gic_redistif_off(void)
|
|
|
|
{
|
|
|
|
gicv3_rdistif_off(plat_my_core_pos());
|
|
|
|
}
|
2017-10-11 16:08:58 +01:00
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* ARM common helper to save & restore the GICv3 on resume from system suspend
|
|
|
|
*****************************************************************************/
|
|
|
|
void plat_arm_gic_save(void)
|
|
|
|
{
|
2018-10-12 16:26:20 +01:00
|
|
|
gicv3_redist_ctx_t * const rdist_context =
|
|
|
|
(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
|
|
|
|
gicv3_dist_ctx_t * const dist_context =
|
|
|
|
(gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
|
2017-10-11 16:08:58 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If an ITS is available, save its context before
|
|
|
|
* the Redistributor using:
|
|
|
|
* gicv3_its_save_disable(gits_base, &its_ctx[i])
|
2019-01-11 18:26:51 +00:00
|
|
|
* Additionally, an implementation-defined sequence may
|
2017-10-11 16:08:58 +01:00
|
|
|
* be required to save the whole ITS state.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Save the GIC Redistributors and ITS contexts before the
|
|
|
|
* Distributor context. As we only handle SYSTEM SUSPEND API,
|
|
|
|
* we only need to save the context of the CPU that is issuing
|
|
|
|
* the SYSTEM SUSPEND call, i.e. the current CPU.
|
|
|
|
*/
|
2018-10-12 16:26:20 +01:00
|
|
|
gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
|
2017-10-11 16:08:58 +01:00
|
|
|
|
|
|
|
/* Save the GIC Distributor context */
|
2018-10-12 16:26:20 +01:00
|
|
|
gicv3_distif_save(dist_context);
|
2017-10-11 16:08:58 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* From here, all the components of the GIC can be safely powered down
|
|
|
|
* as long as there is an alternate way to handle wakeup interrupt
|
|
|
|
* sources.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
void plat_arm_gic_resume(void)
|
|
|
|
{
|
2018-10-12 16:26:20 +01:00
|
|
|
const gicv3_redist_ctx_t *rdist_context =
|
|
|
|
(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
|
|
|
|
const gicv3_dist_ctx_t *dist_context =
|
|
|
|
(gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
|
|
|
|
|
2017-10-11 16:08:58 +01:00
|
|
|
/* Restore the GIC Distributor context */
|
2018-10-12 16:26:20 +01:00
|
|
|
gicv3_distif_init_restore(dist_context);
|
2017-10-11 16:08:58 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Restore the GIC Redistributor and ITS contexts after the
|
|
|
|
* Distributor context. As we only handle SYSTEM SUSPEND API,
|
|
|
|
* we only need to restore the context of the CPU that issued
|
|
|
|
* the SYSTEM SUSPEND call.
|
|
|
|
*/
|
2018-10-12 16:26:20 +01:00
|
|
|
gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
|
2017-10-11 16:08:58 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If an ITS is available, restore its context after
|
|
|
|
* the Redistributor using:
|
|
|
|
* gicv3_its_restore(gits_base, &its_ctx[i])
|
|
|
|
* An implementation-defined sequence may be required to
|
|
|
|
* restore the whole ITS state. The ITS must also be
|
|
|
|
* re-enabled after this sequence has been executed.
|
|
|
|
*/
|
|
|
|
}
|