2017-01-02 14:13:45 +00:00
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/*
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2017-12-19 07:00:05 +00:00
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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2017-01-02 14:13:45 +00:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2019-10-25 00:06:12 +01:00
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#include <assert.h>
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#include <common/bl_common.h>
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#include <mce.h>
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2017-01-02 14:13:45 +00:00
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#include <memctrl_v2.h>
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2019-10-25 00:06:12 +01:00
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#include <tegra_mc_def.h>
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#include <tegra_platform.h>
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2017-01-02 14:13:45 +00:00
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2018-08-03 11:18:15 +01:00
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/*******************************************************************************
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* Array to hold MC context for Tegra194
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******************************************************************************/
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static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
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_START_OF_TABLE_,
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mc_smmu_bypass_cfg, /* TBU settings */
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_END_OF_TABLE_,
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};
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/*******************************************************************************
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* Handler to return the pointer to the MC's context struct
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******************************************************************************/
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static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void)
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{
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/* index of _END_OF_TABLE_ */
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tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U;
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return tegra194_mc_context;
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}
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2017-05-31 19:41:00 +01:00
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/*******************************************************************************
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* Struct to hold the memory controller settings
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******************************************************************************/
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static tegra_mc_settings_t tegra194_mc_settings = {
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2018-08-03 11:18:15 +01:00
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.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx
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2017-05-31 19:41:00 +01:00
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};
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/*******************************************************************************
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* Handler to return the pointer to the memory controller's settings struct
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******************************************************************************/
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tegra_mc_settings_t *tegra_get_mc_settings(void)
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{
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return &tegra194_mc_settings;
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2017-11-14 11:12:58 +00:00
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}
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/*******************************************************************************
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* Handler to program the scratch registers with TZDRAM settings for the
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* resume firmware
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******************************************************************************/
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void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
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{
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2017-11-30 03:53:29 +00:00
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uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
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2019-04-23 00:12:30 +01:00
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uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000;
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uint32_t phys_base_hi = (uint32_t)(phys_base >> 32);
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2017-11-30 03:53:29 +00:00
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2017-11-14 11:12:58 +00:00
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/*
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2017-11-30 03:53:29 +00:00
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* Check TZDRAM carveout register access status. Setup TZDRAM fence
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* only if access is enabled.
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2017-11-14 11:12:58 +00:00
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*/
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2017-11-30 03:53:29 +00:00
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if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
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SECURITY_CFG_WRITE_ACCESS_ENABLE) {
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2017-11-14 11:12:58 +00:00
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Configuring TrustZone DRAM Memory Carveout\n");
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2019-04-23 00:12:30 +01:00
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tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo);
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tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi);
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2017-11-14 11:12:58 +00:00
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tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
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/*
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* MCE propagates the security configuration values across the
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* CCPLEX.
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*/
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(void)mce_update_gsc_tzdram();
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}
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}
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