2014-02-18 18:09:12 +00:00
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/*
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2019-02-26 11:41:03 +00:00
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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2014-02-18 18:09:12 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2014-02-18 18:09:12 +00:00
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*/
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#include <arch.h>
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2014-03-18 13:46:55 +00:00
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#include <asm_macros.S>
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2018-12-14 00:18:21 +00:00
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#include <bl32/tsp/tsp.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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2014-08-01 17:58:27 +01:00
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#include "../tsp_private.h"
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2014-02-18 18:09:12 +00:00
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.globl tsp_entrypoint
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2014-05-20 21:43:27 +01:00
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.globl tsp_vector_table
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2014-02-18 18:09:12 +00:00
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2014-05-09 20:49:17 +01:00
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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* Populate the params in x0-x7 from the pointer
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* to the smc args structure in x0.
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* ---------------------------------------------
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*/
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.macro restore_args_call_smc
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ldp x6, x7, [x0, #TSP_ARG6]
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ldp x4, x5, [x0, #TSP_ARG4]
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ldp x2, x3, [x0, #TSP_ARG2]
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ldp x0, x1, [x0, #TSP_ARG0]
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smc #0
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.endm
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2014-05-09 11:42:56 +01:00
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.macro save_eret_context reg1 reg2
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mrs \reg1, elr_el1
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mrs \reg2, spsr_el1
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stp \reg1, \reg2, [sp, #-0x10]!
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stp x30, x18, [sp, #-0x10]!
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.endm
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.macro restore_eret_context reg1 reg2
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ldp x30, x18, [sp], #0x10
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ldp \reg1, \reg2, [sp], #0x10
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msr elr_el1, \reg1
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msr spsr_el1, \reg2
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.endm
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Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.
An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:
[...]
endfunc plat_crash_console_putc
.align 16
func platform_cpu_warmboot
[...]
This assembles into the following plat_helpers.o:
Sections:
Idx Name Size [...] Algn
9 .text.plat_crash_console_putc 00010000 [...] 2**16
10 .text.platform_cpu_warmboot 00000080 [...] 2**3
As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).
There's no real way to fix this with the existing func macro. Code like
func myfunc
.align X
happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.
Also fix up all existing instances of this dangerous antipattern.
Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-08-01 23:16:36 +01:00
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func tsp_entrypoint _align=3
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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2014-05-09 12:17:56 +01:00
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adr x0, tsp_exceptions
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2014-02-18 18:09:12 +00:00
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msr vbar_el1, x0
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2014-08-04 23:13:10 +01:00
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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2014-07-18 18:38:28 +01:00
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* Enable the instruction cache, stack pointer
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2019-03-04 16:42:54 +00:00
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* and data access alignment checks and disable
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* speculative loads.
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2014-02-18 18:09:12 +00:00
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* ---------------------------------------------
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*/
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2014-07-18 18:38:28 +01:00
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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2014-02-18 18:09:12 +00:00
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mrs x0, sctlr_el1
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2014-07-18 18:38:28 +01:00
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orr x0, x0, x1
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2019-03-04 16:42:54 +00:00
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bic x0, x0, #SCTLR_DSSBS_BIT
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2014-02-18 18:09:12 +00:00
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msr sctlr_el1, x0
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isb
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2015-09-11 16:03:13 +01:00
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/* ---------------------------------------------
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* Invalidate the RW memory used by the BL32
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* image. This includes the data and NOBITS
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* sections. This is done to safeguard against
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* possible corruption of this memory by dirty
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* cache lines in a system cache as a result of
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* use by an earlier boot loader stage.
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* ---------------------------------------------
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*/
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adr x0, __RW_START__
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adr x1, __RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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2016-12-02 13:51:54 +00:00
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bl zeromem
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2014-02-18 18:09:12 +00:00
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2015-01-08 18:02:44 +00:00
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#if USE_COHERENT_MEM
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2014-02-18 18:09:12 +00:00
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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2016-12-02 13:51:54 +00:00
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bl zeromem
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2015-01-08 18:02:44 +00:00
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#endif
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2014-02-18 18:09:12 +00:00
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/* --------------------------------------------
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2014-06-25 19:26:22 +01:00
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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2014-02-18 18:09:12 +00:00
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* --------------------------------------------
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*/
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2015-07-08 21:45:46 +01:00
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bl plat_set_my_stack
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2014-02-18 18:09:12 +00:00
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2017-02-24 18:14:15 +00:00
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/* ---------------------------------------------
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* Initialize the stack protector canary before
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* any C code is called.
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* ---------------------------------------------
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*/
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#if STACK_PROTECTOR_ENABLED
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bl update_stack_protector_canary
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#endif
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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2019-02-26 11:41:03 +00:00
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* Perform TSP setup
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2014-02-18 18:09:12 +00:00
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* ---------------------------------------------
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*/
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2019-02-26 11:41:03 +00:00
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bl tsp_setup
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#if ENABLE_PAUTH
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2019-05-24 12:17:09 +01:00
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/* ---------------------------------------------
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2019-09-13 14:11:59 +01:00
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* Program APIAKey_EL1
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* and enable pointer authentication
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2019-05-24 12:17:09 +01:00
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* ---------------------------------------------
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*/
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2019-09-13 14:11:59 +01:00
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bl pauth_init_enable_el1
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2019-02-26 11:41:03 +00:00
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#endif /* ENABLE_PAUTH */
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl tsp_main
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/* ---------------------------------------------
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* Tell TSPD that we are done initialising
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* ---------------------------------------------
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*/
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mov x1, x0
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mov x0, #TSP_ENTRY_DONE
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smc #0
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tsp_entrypoint_panic:
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b tsp_entrypoint_panic
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2015-03-24 14:03:57 +00:00
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endfunc tsp_entrypoint
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2014-02-18 18:09:12 +00:00
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2014-05-20 21:43:27 +01:00
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/* -------------------------------------------
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* Table of entrypoint vectors provided to the
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* TSPD for the various entrypoints
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* -------------------------------------------
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*/
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2019-05-24 12:17:09 +01:00
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vector_base tsp_vector_table
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2017-04-05 11:34:03 +01:00
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b tsp_yield_smc_entry
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2014-05-20 21:43:27 +01:00
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b tsp_fast_smc_entry
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b tsp_cpu_on_entry
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b tsp_cpu_off_entry
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b tsp_cpu_resume_entry
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b tsp_cpu_suspend_entry
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2015-09-03 18:29:38 +01:00
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b tsp_sel1_intr_entry
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2014-08-12 11:17:06 +01:00
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b tsp_system_off_entry
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b tsp_system_reset_entry
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2017-04-05 11:34:03 +01:00
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b tsp_abort_yield_smc_entry
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2014-05-20 21:43:27 +01:00
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2014-02-18 18:09:12 +00:00
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is to be turned off through a CPU_OFF
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* psci call to ask the TSP to perform any
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* bookeeping necessary. In the current
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* implementation, the TSPD expects the TSP to
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* re-initialise its state so nothing is done
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* here except for acknowledging the request.
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* ---------------------------------------------
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*/
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2014-03-18 13:46:55 +00:00
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func tsp_cpu_off_entry
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2014-02-18 18:09:12 +00:00
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bl tsp_cpu_off_main
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restore_args_call_smc
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2015-03-24 14:03:57 +00:00
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endfunc tsp_cpu_off_entry
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2014-02-18 18:09:12 +00:00
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2014-08-12 11:17:06 +01:00
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when the
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* system is about to be switched off (through
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* a SYSTEM_OFF psci call) to ask the TSP to
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* perform any necessary bookkeeping.
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* ---------------------------------------------
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*/
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func tsp_system_off_entry
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bl tsp_system_off_main
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restore_args_call_smc
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2015-03-24 14:03:57 +00:00
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endfunc tsp_system_off_entry
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2014-08-12 11:17:06 +01:00
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when the
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* system is about to be reset (through a
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* SYSTEM_RESET psci call) to ask the TSP to
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* perform any necessary bookkeeping.
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* ---------------------------------------------
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*/
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func tsp_system_reset_entry
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bl tsp_system_reset_main
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restore_args_call_smc
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2015-03-24 14:03:57 +00:00
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endfunc tsp_system_reset_entry
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2014-08-12 11:17:06 +01:00
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2014-02-18 18:09:12 +00:00
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is turned on using a CPU_ON psci call to
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* ask the TSP to initialise itself i.e. setup
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* the mmu, stacks etc. Minimal architectural
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* state will be initialised by the TSPD when
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* this function is entered i.e. Caches and MMU
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* will be turned off, the execution state
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* will be aarch64 and exceptions masked.
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* ---------------------------------------------
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*/
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2014-03-18 13:46:55 +00:00
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func tsp_cpu_on_entry
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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2014-05-09 12:17:56 +01:00
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adr x0, tsp_exceptions
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2014-02-18 18:09:12 +00:00
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msr vbar_el1, x0
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2014-08-04 23:13:10 +01:00
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isb
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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2014-07-18 18:38:28 +01:00
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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2014-02-18 18:09:12 +00:00
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* ---------------------------------------------
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*/
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2014-07-18 18:38:28 +01:00
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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2014-02-18 18:09:12 +00:00
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mrs x0, sctlr_el1
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2014-07-18 18:38:28 +01:00
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orr x0, x0, x1
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2014-02-18 18:09:12 +00:00
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msr sctlr_el1, x0
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isb
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/* --------------------------------------------
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2014-06-26 09:58:52 +01:00
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* Give ourselves a stack whose memory will be
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* marked as Normal-IS-WBWA when the MMU is
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* enabled.
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2014-02-18 18:09:12 +00:00
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* --------------------------------------------
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*/
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2015-07-08 21:45:46 +01:00
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bl plat_set_my_stack
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2014-02-18 18:09:12 +00:00
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2014-06-26 09:58:52 +01:00
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/* --------------------------------------------
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2018-04-27 16:28:12 +01:00
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* Enable MMU and D-caches together.
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2014-06-26 09:58:52 +01:00
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* --------------------------------------------
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2014-02-18 18:09:12 +00:00
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*/
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2018-04-27 16:28:12 +01:00
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mov x0, #0
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2014-05-16 14:08:45 +01:00
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bl bl32_plat_enable_mmu
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2014-02-18 18:09:12 +00:00
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2019-09-13 14:11:59 +01:00
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1
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* and enable pointer authentication
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el1
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#endif /* ENABLE_PAUTH */
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2014-02-18 18:09:12 +00:00
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/* ---------------------------------------------
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* Enter C runtime to perform any remaining
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* book keeping
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* ---------------------------------------------
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*/
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bl tsp_cpu_on_main
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restore_args_call_smc
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/* Should never reach here */
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tsp_cpu_on_entry_panic:
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b tsp_cpu_on_entry_panic
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2015-03-24 14:03:57 +00:00
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endfunc tsp_cpu_on_entry
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2014-02-18 18:09:12 +00:00
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is to be suspended through a CPU_SUSPEND
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* psci call to ask the TSP to perform any
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|
* bookeeping necessary. In the current
|
|
|
|
* implementation, the TSPD saves and restores
|
|
|
|
* the EL1 state.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
2014-03-18 13:46:55 +00:00
|
|
|
func tsp_cpu_suspend_entry
|
2014-02-18 18:09:12 +00:00
|
|
|
bl tsp_cpu_suspend_main
|
|
|
|
restore_args_call_smc
|
2015-03-24 14:03:57 +00:00
|
|
|
endfunc tsp_cpu_suspend_entry
|
2014-02-18 18:09:12 +00:00
|
|
|
|
2015-09-03 18:29:38 +01:00
|
|
|
/*-------------------------------------------------
|
2014-05-09 11:42:56 +01:00
|
|
|
* This entrypoint is used by the TSPD to pass
|
2015-11-13 02:08:43 +00:00
|
|
|
* control for `synchronously` handling a S-EL1
|
|
|
|
* Interrupt which was triggered while executing
|
|
|
|
* in normal world. 'x0' contains a magic number
|
|
|
|
* which indicates this. TSPD expects control to
|
|
|
|
* be handed back at the end of interrupt
|
|
|
|
* processing. This is done through an SMC.
|
|
|
|
* The handover agreement is:
|
2014-05-09 11:42:56 +01:00
|
|
|
*
|
|
|
|
* 1. PSTATE.DAIF are set upon entry. 'x1' has
|
|
|
|
* the ELR_EL3 from the non-secure state.
|
|
|
|
* 2. TSP has to preserve the callee saved
|
|
|
|
* general purpose registers, SP_EL1/EL0 and
|
|
|
|
* LR.
|
|
|
|
* 3. TSP has to preserve the system and vfp
|
|
|
|
* registers (if applicable).
|
|
|
|
* 4. TSP can use 'x0-x18' to enable its C
|
|
|
|
* runtime.
|
|
|
|
* 5. TSP returns to TSPD using an SMC with
|
2015-09-03 18:29:38 +01:00
|
|
|
* 'x0' = TSP_HANDLED_S_EL1_INTR
|
|
|
|
* ------------------------------------------------
|
2014-05-09 11:42:56 +01:00
|
|
|
*/
|
2015-09-03 18:29:38 +01:00
|
|
|
func tsp_sel1_intr_entry
|
2014-05-09 11:42:56 +01:00
|
|
|
#if DEBUG
|
2015-11-13 02:08:43 +00:00
|
|
|
mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN
|
2014-05-09 11:42:56 +01:00
|
|
|
cmp x0, x2
|
2015-09-03 18:29:38 +01:00
|
|
|
b.ne tsp_sel1_int_entry_panic
|
2014-05-09 11:42:56 +01:00
|
|
|
#endif
|
2015-09-03 18:29:38 +01:00
|
|
|
/*-------------------------------------------------
|
2014-05-09 11:42:56 +01:00
|
|
|
* Save any previous context needed to perform
|
|
|
|
* an exception return from S-EL1 e.g. context
|
2015-09-03 18:29:38 +01:00
|
|
|
* from a previous Non secure Interrupt.
|
|
|
|
* Update statistics and handle the S-EL1
|
|
|
|
* interrupt before returning to the TSPD.
|
2014-05-09 11:42:56 +01:00
|
|
|
* IRQ/FIQs are not enabled since that will
|
|
|
|
* complicate the implementation. Execution
|
|
|
|
* will be transferred back to the normal world
|
2015-11-13 02:08:43 +00:00
|
|
|
* in any case. The handler can return 0
|
|
|
|
* if the interrupt was handled or TSP_PREEMPTED
|
|
|
|
* if the expected interrupt was preempted
|
|
|
|
* by an interrupt that should be handled in EL3
|
|
|
|
* e.g. Group 0 interrupt in GICv3. In both
|
|
|
|
* the cases switch to EL3 using SMC with id
|
|
|
|
* TSP_HANDLED_S_EL1_INTR. Any other return value
|
|
|
|
* from the handler will result in panic.
|
2015-09-03 18:29:38 +01:00
|
|
|
* ------------------------------------------------
|
2014-05-09 11:42:56 +01:00
|
|
|
*/
|
|
|
|
save_eret_context x2 x3
|
2015-09-03 18:29:38 +01:00
|
|
|
bl tsp_update_sync_sel1_intr_stats
|
|
|
|
bl tsp_common_int_handler
|
2015-11-13 02:08:43 +00:00
|
|
|
/* Check if the S-EL1 interrupt has been handled */
|
|
|
|
cbnz x0, tsp_sel1_intr_check_preemption
|
|
|
|
b tsp_sel1_intr_return
|
|
|
|
tsp_sel1_intr_check_preemption:
|
|
|
|
/* Check if the S-EL1 interrupt has been preempted */
|
|
|
|
mov_imm x1, TSP_PREEMPTED
|
|
|
|
cmp x0, x1
|
|
|
|
b.ne tsp_sel1_int_entry_panic
|
|
|
|
tsp_sel1_intr_return:
|
|
|
|
mov_imm x0, TSP_HANDLED_S_EL1_INTR
|
2014-05-09 11:42:56 +01:00
|
|
|
restore_eret_context x2 x3
|
|
|
|
smc #0
|
|
|
|
|
2015-11-13 02:08:43 +00:00
|
|
|
/* Should never reach here */
|
2015-09-03 18:29:38 +01:00
|
|
|
tsp_sel1_int_entry_panic:
|
2016-11-30 15:21:11 +00:00
|
|
|
no_ret plat_panic_handler
|
2015-09-03 18:29:38 +01:00
|
|
|
endfunc tsp_sel1_intr_entry
|
2014-05-09 11:42:56 +01:00
|
|
|
|
2014-02-18 18:09:12 +00:00
|
|
|
/*---------------------------------------------
|
|
|
|
* This entrypoint is used by the TSPD when this
|
|
|
|
* cpu resumes execution after an earlier
|
|
|
|
* CPU_SUSPEND psci call to ask the TSP to
|
|
|
|
* restore its saved context. In the current
|
|
|
|
* implementation, the TSPD saves and restores
|
|
|
|
* EL1 state so nothing is done here apart from
|
|
|
|
* acknowledging the request.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
2014-03-18 13:46:55 +00:00
|
|
|
func tsp_cpu_resume_entry
|
2014-02-18 18:09:12 +00:00
|
|
|
bl tsp_cpu_resume_main
|
|
|
|
restore_args_call_smc
|
2016-02-01 13:57:25 +00:00
|
|
|
|
|
|
|
/* Should never reach here */
|
2016-11-30 15:21:11 +00:00
|
|
|
no_ret plat_panic_handler
|
2015-03-24 14:03:57 +00:00
|
|
|
endfunc tsp_cpu_resume_entry
|
2014-02-18 18:09:12 +00:00
|
|
|
|
|
|
|
/*---------------------------------------------
|
|
|
|
* This entrypoint is used by the TSPD to ask
|
|
|
|
* the TSP to service a fast smc request.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
2014-03-18 13:46:55 +00:00
|
|
|
func tsp_fast_smc_entry
|
2014-05-09 20:49:17 +01:00
|
|
|
bl tsp_smc_handler
|
2014-02-18 18:09:12 +00:00
|
|
|
restore_args_call_smc
|
2016-02-01 13:57:25 +00:00
|
|
|
|
|
|
|
/* Should never reach here */
|
2016-11-30 15:21:11 +00:00
|
|
|
no_ret plat_panic_handler
|
2015-03-24 14:03:57 +00:00
|
|
|
endfunc tsp_fast_smc_entry
|
2014-02-18 18:09:12 +00:00
|
|
|
|
2014-05-09 20:49:17 +01:00
|
|
|
/*---------------------------------------------
|
|
|
|
* This entrypoint is used by the TSPD to ask
|
2017-04-05 11:34:03 +01:00
|
|
|
* the TSP to service a Yielding SMC request.
|
2014-05-09 20:49:17 +01:00
|
|
|
* We will enable preemption during execution
|
|
|
|
* of tsp_smc_handler.
|
|
|
|
* ---------------------------------------------
|
|
|
|
*/
|
2017-04-05 11:34:03 +01:00
|
|
|
func tsp_yield_smc_entry
|
2014-05-09 20:49:17 +01:00
|
|
|
msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
|
|
|
|
bl tsp_smc_handler
|
|
|
|
msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
|
|
|
|
restore_args_call_smc
|
2016-02-01 13:57:25 +00:00
|
|
|
|
|
|
|
/* Should never reach here */
|
2016-11-30 15:21:11 +00:00
|
|
|
no_ret plat_panic_handler
|
2017-04-05 11:34:03 +01:00
|
|
|
endfunc tsp_yield_smc_entry
|
2016-11-24 15:43:19 +00:00
|
|
|
|
|
|
|
/*---------------------------------------------------------------------
|
2017-04-05 11:34:03 +01:00
|
|
|
* This entrypoint is used by the TSPD to abort a pre-empted Yielding
|
2016-11-24 15:43:19 +00:00
|
|
|
* SMC. It could be on behalf of non-secure world or because a CPU
|
|
|
|
* suspend/CPU off request needs to abort the preempted SMC.
|
|
|
|
* --------------------------------------------------------------------
|
|
|
|
*/
|
2017-04-05 11:34:03 +01:00
|
|
|
func tsp_abort_yield_smc_entry
|
2016-11-24 15:43:19 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Exceptions masking is already done by the TSPD when entering this
|
|
|
|
* hook so there is no need to do it here.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Reset the stack used by the pre-empted SMC */
|
|
|
|
bl plat_set_my_stack
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allow some cleanup such as releasing locks.
|
|
|
|
*/
|
|
|
|
bl tsp_abort_smc_handler
|
|
|
|
|
|
|
|
restore_args_call_smc
|
|
|
|
|
|
|
|
/* Should never reach here */
|
|
|
|
bl plat_panic_handler
|
2017-04-05 11:34:03 +01:00
|
|
|
endfunc tsp_abort_yield_smc_entry
|