2017-03-08 14:40:23 +00:00
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/*
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2018-05-02 11:23:56 +01:00
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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2017-03-08 14:40:23 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2017-03-08 14:40:23 +00:00
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <cassert.h>
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#include <sys/types.h>
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2017-08-07 11:20:13 +01:00
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#include <utils_def.h>
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2017-03-08 14:40:23 +00:00
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#include <xlat_tables_v2.h>
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#include "../xlat_tables_private.h"
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xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
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uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
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2018-06-11 13:40:32 +01:00
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/*
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* Returns 1 if the provided granule size is supported, 0 otherwise.
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*/
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int xlat_arch_is_granule_size_supported(size_t size)
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{
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u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
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if (size == (4U * 1024U)) {
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return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
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ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
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ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
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} else if (size == (16U * 1024U)) {
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return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
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ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
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ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
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} else if (size == (64U * 1024U)) {
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return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
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ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
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ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
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}
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return 0;
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}
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size_t xlat_arch_get_max_supported_granule_size(void)
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{
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if (xlat_arch_is_granule_size_supported(64U * 1024U)) {
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return 64U * 1024U;
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} else if (xlat_arch_is_granule_size_supported(16U * 1024U)) {
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return 16U * 1024U;
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} else {
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assert(xlat_arch_is_granule_size_supported(4U * 1024U));
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return 4U * 1024U;
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}
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}
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2017-10-25 11:53:25 +01:00
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unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr)
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2017-03-08 14:40:23 +00:00
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{
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/* Physical address can't exceed 48 bits */
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assert((max_addr & ADDR_MASK_48_TO_63) == 0);
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/* 48 bits address */
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if (max_addr & ADDR_MASK_44_TO_47)
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return TCR_PS_BITS_256TB;
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/* 44 bits address */
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if (max_addr & ADDR_MASK_42_TO_43)
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return TCR_PS_BITS_16TB;
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/* 42 bits address */
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if (max_addr & ADDR_MASK_40_TO_41)
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return TCR_PS_BITS_4TB;
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/* 40 bits address */
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if (max_addr & ADDR_MASK_36_TO_39)
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return TCR_PS_BITS_1TB;
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/* 36 bits address */
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if (max_addr & ADDR_MASK_32_TO_35)
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return TCR_PS_BITS_64GB;
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return TCR_PS_BITS_4GB;
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}
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2017-03-22 15:48:51 +00:00
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#if ENABLE_ASSERTIONS
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2018-05-02 11:23:56 +01:00
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/*
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* Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is
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* supported in ARMv8.2 onwards.
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*/
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2017-03-08 14:40:23 +00:00
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static const unsigned int pa_range_bits_arr[] = {
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PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
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2018-05-02 11:23:56 +01:00
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PARANGE_0101, PARANGE_0110
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2017-03-08 14:40:23 +00:00
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};
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2017-05-31 13:31:48 +01:00
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unsigned long long xlat_arch_get_max_supported_pa(void)
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2017-03-08 14:40:23 +00:00
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{
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u_register_t pa_range = read_id_aa64mmfr0_el1() &
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ID_AA64MMFR0_EL1_PARANGE_MASK;
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/* All other values are reserved */
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assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
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2018-02-16 21:12:58 +00:00
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return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
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2017-03-08 14:40:23 +00:00
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}
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2017-03-22 15:48:51 +00:00
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#endif /* ENABLE_ASSERTIONS*/
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2017-03-08 14:40:23 +00:00
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2017-10-04 16:52:15 +01:00
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int is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
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2017-03-08 14:40:23 +00:00
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{
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2017-10-04 16:52:15 +01:00
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if (ctx->xlat_regime == EL1_EL0_REGIME) {
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assert(xlat_arch_current_el() >= 1);
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return (read_sctlr_el1() & SCTLR_M_BIT) != 0;
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} else {
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assert(ctx->xlat_regime == EL3_REGIME);
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assert(xlat_arch_current_el() >= 3);
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return (read_sctlr_el3() & SCTLR_M_BIT) != 0;
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}
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2017-03-08 14:40:23 +00:00
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}
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2018-07-05 08:11:48 +01:00
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uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime)
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{
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if (xlat_regime == EL1_EL0_REGIME) {
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return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN);
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} else {
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assert(xlat_regime == EL3_REGIME);
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return UPPER_ATTRS(XN);
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}
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}
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2017-10-04 16:52:15 +01:00
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2018-07-11 09:46:45 +01:00
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void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime)
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2017-02-27 17:23:54 +00:00
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{
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/*
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* Ensure the translation table write has drained into memory before
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* invalidating the TLB entry.
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*/
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dsbishst();
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2017-09-25 15:23:22 +01:00
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/*
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* This function only supports invalidation of TLB entries for the EL3
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* and EL1&0 translation regimes.
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*
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* Also, it is architecturally UNDEFINED to invalidate TLBs of a higher
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* exception level (see section D4.9.2 of the ARM ARM rev B.a).
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*/
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if (xlat_regime == EL1_EL0_REGIME) {
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assert(xlat_arch_current_el() >= 1);
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tlbivaae1is(TLBI_ADDR(va));
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} else {
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assert(xlat_regime == EL3_REGIME);
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assert(xlat_arch_current_el() >= 3);
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tlbivae3is(TLBI_ADDR(va));
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}
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2017-02-27 17:23:54 +00:00
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}
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void xlat_arch_tlbi_va_sync(void)
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{
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/*
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* A TLB maintenance instruction can complete at any time after
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* it is issued, but is only guaranteed to be complete after the
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* execution of DSB by the PE that executed the TLB maintenance
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* instruction. After the TLB invalidate instruction is
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* complete, no new memory accesses using the invalidated TLB
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* entries will be observed by any observer of the system
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* domain. See section D4.8.2 of the ARMv8 (issue k), paragraph
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* "Ordering and completion of TLB maintenance instructions".
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*/
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dsbish();
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/*
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* The effects of a completed TLB maintenance instruction are
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* only guaranteed to be visible on the PE that executed the
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* instruction after the execution of an ISB instruction by the
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* PE that executed the TLB maintenance instruction.
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*/
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isb();
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}
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Fix execute-never permissions in xlat tables libs
Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setting to 1 the XN bit in the Upper Attributes field in the translation
tables descriptors. Translation regimes that support two different
virtual address spaces (such as the one shared by EL1 and EL0) use bits
PXN and UXN instead.
The Trusted Firmware runs at EL3 and EL1, it has to handle translation
tables of both translation regimes, but the previous code handled both
regimes the same way, as if both had only 1 VA range.
When trying to set a descriptor as execute-never it would set the XN
bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is
at the same bit position as UXN, which means that EL0 was being
prevented from executing code at this region, not EL1 as the code
intended. Therefore, the PXN bit was unset to 0 all the time. The result
is that, in AArch64 mode, read-only data sections of BL2 weren't
protected from being executed.
This patch adds support of translation regimes with two virtual address
spaces to both versions of the translation tables library, fixing the
execute-never permissions for translation tables in EL1.
The library currently does not support initializing translation tables
for EL0 software, therefore it does not set/unset the UXN bit. If EL1
software needs to initialize translation tables for EL0 software, it
should use a different library instead.
Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-27 13:30:22 +01:00
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int xlat_arch_current_el(void)
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{
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int el = GET_EL(read_CurrentEl());
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assert(el > 0);
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return el;
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}
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2018-07-12 15:43:07 +01:00
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void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table,
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unsigned long long max_pa, uintptr_t max_va, int xlat_regime)
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2017-03-08 14:40:23 +00:00
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{
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2017-05-31 13:38:51 +01:00
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uint64_t mair, ttbr, tcr;
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xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
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uintptr_t virtual_addr_space_size;
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2017-05-31 13:38:51 +01:00
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/* Set attributes in the right indices of the MAIR. */
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
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ttbr = (uint64_t) base_table;
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/*
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* Limit the input address ranges and memory region sizes translated
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* using TTBR0 to the given virtual address space size.
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*/
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xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
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assert(max_va < ((uint64_t) UINTPTR_MAX));
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virtual_addr_space_size = max_va + 1;
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2017-07-11 15:11:10 +01:00
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assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size));
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xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
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2017-07-11 15:11:10 +01:00
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/*
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2017-07-19 10:11:13 +01:00
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* __builtin_ctzll(0) is undefined but here we are guaranteed that
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2017-07-11 15:11:10 +01:00
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* virtual_addr_space_size is in the range [1,UINTPTR_MAX].
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*/
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xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
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tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size);
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2017-05-31 13:38:51 +01:00
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/*
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* Set the cacheability and shareability attributes for memory
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* associated with translation table walks.
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*/
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xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
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if ((flags & XLAT_TABLE_NC) != 0) {
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2017-05-31 13:38:51 +01:00
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/* Inner & outer non-cacheable non-shareable. */
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tcr |= TCR_SH_NON_SHAREABLE |
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TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC;
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} else {
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|
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/* Inner & outer WBWA & shareable. */
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tcr |= TCR_SH_INNER_SHAREABLE |
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TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA;
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}
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2017-05-31 13:31:48 +01:00
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|
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/*
|
|
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* It is safer to restrict the max physical address accessible by the
|
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* hardware as much as possible.
|
|
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*/
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2017-10-25 11:53:25 +01:00
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unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa);
|
2017-05-31 13:31:48 +01:00
|
|
|
|
2018-07-12 15:43:07 +01:00
|
|
|
if (xlat_regime == EL1_EL0_REGIME) {
|
|
|
|
/*
|
|
|
|
* TCR_EL1.EPD1: Disable translation table walk for addresses
|
|
|
|
* that are translated using TTBR1_EL1.
|
|
|
|
*/
|
|
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|
tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
|
|
|
|
} else {
|
|
|
|
assert(xlat_regime == EL3_REGIME);
|
|
|
|
tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT);
|
|
|
|
}
|
xlat v2: Split MMU setup and enable
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-04-27 15:06:57 +01:00
|
|
|
|
|
|
|
mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair;
|
|
|
|
mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr;
|
|
|
|
|
|
|
|
/* Set TTBR bits as well */
|
|
|
|
if (ARM_ARCH_AT_LEAST(8, 2)) {
|
|
|
|
/*
|
|
|
|
* Enable CnP bit so as to share page tables with all PEs. This
|
|
|
|
* is mandatory for ARMv8.2 implementations.
|
|
|
|
*/
|
|
|
|
ttbr |= TTBR_CNP_BIT;
|
|
|
|
}
|
|
|
|
|
|
|
|
mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr;
|
|
|
|
mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32);
|
2017-03-08 14:40:23 +00:00
|
|
|
}
|