2014-08-12 13:04:43 +01:00
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/*
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2014-05-14 17:44:19 +01:00
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FVP_DEF_H__
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#define __FVP_DEF_H__
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/* Firmware Image Package */
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#define FIP_IMAGE_NAME "fip.bin"
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2014-07-16 15:53:43 +01:00
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#define FVP_PRIMARY_CPU 0x0
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2014-05-14 17:44:19 +01:00
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2014-09-24 10:00:06 +01:00
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/* Memory location options for TSP */
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2014-12-19 09:51:00 +00:00
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#define FVP_TRUSTED_SRAM_ID 0
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#define FVP_TRUSTED_DRAM_ID 1
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#define FVP_DRAM_ID 2
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/*
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* Some of the definitions in this file use the 'ull' suffix in order to avoid
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* subtle integer overflow errors due to implicit integer type promotion when
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* working with 32-bit values.
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*
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* The TSP linker script includes some of these definitions to define the BL3-2
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* memory map, but the GNU LD does not support the 'ull' suffix, causing the
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* build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
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* will add the 'ull' suffix only when the macro __LINKER__ is not defined
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* (__LINKER__ is defined in the command line to preprocess the linker script).
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* Constants in the linker script will not have the 'ull' suffix, but this is
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* not a problem since the linker evaluates all constant expressions to 64 bit
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* (assuming the target architecture is 64 bit).
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*/
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#ifndef __LINKER__
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#define MAKE_ULL(x) x##ull
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#else
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#define MAKE_ULL(x) x
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#endif
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2014-08-12 13:04:43 +01:00
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2014-05-14 17:44:19 +01:00
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/*******************************************************************************
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* FVP memory map related constants
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******************************************************************************/
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2014-08-12 13:04:43 +01:00
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#define FVP_TRUSTED_ROM_BASE 0x00000000
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#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
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2014-09-24 10:00:06 +01:00
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/* The first 4KB of Trusted SRAM are used as shared memory */
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#define FVP_SHARED_MEM_BASE 0x04000000
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#define FVP_SHARED_MEM_SIZE 0x00001000 /* 4 KB */
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/* The remaining Trusted SRAM is used to load the BL images */
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#define FVP_TRUSTED_SRAM_BASE 0x04001000
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#define FVP_TRUSTED_SRAM_SIZE 0x0003F000 /* 252 KB */
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2014-08-12 13:04:43 +01:00
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#define FVP_TRUSTED_DRAM_BASE 0x06000000
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#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
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2014-05-14 17:44:19 +01:00
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#define FLASH0_BASE 0x08000000
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2014-08-12 13:04:43 +01:00
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#define FLASH0_SIZE 0x04000000
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2014-05-14 17:44:19 +01:00
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#define FLASH1_BASE 0x0c000000
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#define FLASH1_SIZE 0x04000000
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#define PSRAM_BASE 0x14000000
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#define PSRAM_SIZE 0x04000000
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#define VRAM_BASE 0x18000000
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#define VRAM_SIZE 0x02000000
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE 0x1a000000
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#define DEVICE0_SIZE 0x12200000
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#define DEVICE1_BASE 0x2f000000
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#define DEVICE1_SIZE 0x200000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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2014-12-19 09:51:00 +00:00
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#define DRAM1_BASE MAKE_ULL(0x80000000)
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#define DRAM1_SIZE MAKE_ULL(0x80000000)
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2014-05-14 17:44:19 +01:00
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#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
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2014-12-19 09:28:30 +00:00
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/* Define the top 16 MB of DRAM1 as secure */
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2014-12-19 09:51:00 +00:00
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#define DRAM1_SEC_SIZE MAKE_ULL(0x01000000)
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2014-12-19 09:28:30 +00:00
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#define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE)
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#define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1)
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#define DRAM1_NS_BASE DRAM1_BASE
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#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE)
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#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1)
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2014-05-14 17:44:19 +01:00
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#define DRAM_BASE DRAM1_BASE
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#define DRAM_SIZE DRAM1_SIZE
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2014-12-19 09:51:00 +00:00
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#define DRAM2_BASE MAKE_ULL(0x880000000)
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#define DRAM2_SIZE MAKE_ULL(0x780000000)
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2014-05-14 17:44:19 +01:00
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#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
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#define PCIE_EXP_BASE 0x40000000
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#define TZRNG_BASE 0x7fe60000
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#define TZNVCTR_BASE 0x7fe70000
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#define TZROOTKEY_BASE 0x7fe80000
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/* Memory mapped Generic timer interfaces */
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#define SYS_CNTCTL_BASE 0x2a430000
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#define SYS_CNTREAD_BASE 0x2a800000
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#define SYS_TIMCTL_BASE 0x2a810000
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/* V2M motherboard system registers & offsets */
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#define VE_SYSREGS_BASE 0x1c010000
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2014-08-12 11:17:06 +01:00
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#define V2M_SYS_ID 0x0
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#define V2M_SYS_SWITCH 0x4
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#define V2M_SYS_LED 0x8
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2014-05-14 17:44:19 +01:00
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#define V2M_SYS_CFGDATA 0xa0
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#define V2M_SYS_CFGCTRL 0xa4
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2014-08-12 11:17:06 +01:00
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#define V2M_SYS_CFGSTATUS 0xa8
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#define CFGCTRL_START (1 << 31)
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#define CFGCTRL_RW (1 << 30)
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#define CFGCTRL_FUNC_SHIFT 20
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#define CFGCTRL_FUNC(fn) (fn << CFGCTRL_FUNC_SHIFT)
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#define FUNC_CLK_GEN 0x01
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#define FUNC_TEMP 0x04
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#define FUNC_DB_RESET 0x05
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#define FUNC_SCC_CFG 0x06
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#define FUNC_SHUTDOWN 0x08
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#define FUNC_REBOOT 0x09
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2014-05-14 17:44:19 +01:00
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2015-01-22 11:22:22 +00:00
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#if USE_COHERENT_MEM
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#define FVP_BL_REGIONS 3
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#else
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#define FVP_BL_REGIONS 2
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#endif
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/*
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* The FVP_MAX_MMAP_REGIONS depend on the number of entries in fvp_mmap[]
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* defined for each BL stage in fvp_common.c.
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*/
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#if IMAGE_BL1
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#define FVP_MMAP_ENTRIES 5
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#endif
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#if IMAGE_BL2
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#define FVP_MMAP_ENTRIES 7
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#endif
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#if IMAGE_BL31
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#define FVP_MMAP_ENTRIES 4
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#endif
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#if IMAGE_BL32
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#define FVP_MMAP_ENTRIES 3
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#endif
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2014-05-14 17:44:19 +01:00
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/* Load address of BL33 in the FVP port */
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#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
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2014-05-28 22:22:55 +01:00
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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2014-05-14 17:44:19 +01:00
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/*
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* V2M sysled bit definitions. The values written to this
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* register are defined in arch.h & runtime_svc.h. Only
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* used by the primary cpu to diagnose any cold boot issues.
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*
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* SYS_LED[0] - Security state (S=0/NS=1)
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* SYS_LED[2:1] - Exception Level (EL3-EL0)
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* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
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*
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*/
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#define SYS_LED_SS_SHIFT 0x0
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#define SYS_LED_EL_SHIFT 0x1
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#define SYS_LED_EC_SHIFT 0x3
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#define SYS_LED_SS_MASK 0x1
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#define SYS_LED_EL_MASK 0x3
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#define SYS_LED_EC_MASK 0x1f
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/* V2M sysid register bits */
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2014-06-13 17:10:00 +01:00
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#define SYS_ID_REV_SHIFT 28
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2014-05-14 17:44:19 +01:00
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#define SYS_ID_HBI_SHIFT 16
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#define SYS_ID_BLD_SHIFT 12
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#define SYS_ID_ARCH_SHIFT 8
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#define SYS_ID_FPGA_SHIFT 0
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#define SYS_ID_REV_MASK 0xf
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#define SYS_ID_HBI_MASK 0xfff
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#define SYS_ID_BLD_MASK 0xf
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#define SYS_ID_ARCH_MASK 0xf
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#define SYS_ID_FPGA_MASK 0xff
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#define SYS_ID_BLD_LENGTH 4
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#define HBI_FVP_BASE 0x020
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2014-06-26 14:27:26 +01:00
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#define REV_FVP_BASE_V0 0x0
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2014-05-14 17:44:19 +01:00
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#define HBI_FOUNDATION 0x010
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2014-06-26 14:27:26 +01:00
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#define REV_FOUNDATION_V2_0 0x0
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#define REV_FOUNDATION_V2_1 0x1
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2014-05-14 17:44:19 +01:00
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#define BLD_GIC_VE_MMAP 0x0
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#define BLD_GIC_A53A57_MMAP 0x1
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#define ARCH_MODEL 0x1
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/* FVP Power controller base address*/
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#define PWRC_BASE 0x1c100000
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define CCI400_BASE 0x2c090000
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2015-02-26 15:25:58 +00:00
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#define CCI400_CLUSTER0_SL_IFACE_IX 3
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#define CCI400_CLUSTER1_SL_IFACE_IX 4
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2014-05-14 17:44:19 +01:00
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* VE compatible GIC memory map */
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#define VE_GICD_BASE 0x2c001000
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#define VE_GICC_BASE 0x2c002000
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#define VE_GICH_BASE 0x2c004000
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#define VE_GICV_BASE 0x2c006000
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/* Base FVP compatible GIC memory map */
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#define BASE_GICD_BASE 0x2f000000
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#define BASE_GICR_BASE 0x2f100000
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#define BASE_GICC_BASE 0x2c000000
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#define BASE_GICH_BASE 0x2c010000
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#define BASE_GICV_BASE 0x2c02f000
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#define IRQ_TZ_WDOG 56
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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/*******************************************************************************
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* PL011 related constants
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******************************************************************************/
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#define PL011_UART0_BASE 0x1c090000
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#define PL011_UART1_BASE 0x1c0a0000
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#define PL011_UART2_BASE 0x1c0b0000
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#define PL011_UART3_BASE 0x1c0c0000
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2014-07-14 15:43:21 +01:00
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#define PL011_BAUDRATE 115200
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#define PL011_UART0_CLK_IN_HZ 24000000
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#define PL011_UART1_CLK_IN_HZ 24000000
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#define PL011_UART2_CLK_IN_HZ 24000000
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#define PL011_UART3_CLK_IN_HZ 24000000
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2014-05-14 17:44:19 +01:00
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/*******************************************************************************
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* TrustZone address space controller related constants
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******************************************************************************/
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#define TZC400_BASE 0x2a4a0000
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/*
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* The NSAIDs for this platform as used to program the TZC400.
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*/
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/* NSAIDs used by devices in TZC filter 0 on FVP */
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#define FVP_NSAID_DEFAULT 0
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#define FVP_NSAID_PCI 1
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#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
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#define FVP_NSAID_AP 9 /* Application Processors */
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#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
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/* NSAIDs used by devices in TZC filter 2 on FVP */
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#define FVP_NSAID_HDLCD0 2
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#define FVP_NSAID_CLCD 7
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2014-08-12 13:51:51 +01:00
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/*******************************************************************************
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* Shared Data
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******************************************************************************/
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/* Entrypoint mailboxes */
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2014-09-24 10:00:06 +01:00
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#define MBOX_BASE FVP_SHARED_MEM_BASE
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2014-08-12 13:51:51 +01:00
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#define MBOX_SIZE 0x200
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
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2014-05-14 17:44:19 +01:00
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#endif /* __FVP_DEF_H__ */
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