2016-06-30 15:11:07 +01:00
|
|
|
/*
|
2018-04-27 15:06:57 +01:00
|
|
|
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
|
2016-06-30 15:11:07 +01:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2016-06-30 15:11:07 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <arch.h>
|
|
|
|
#include <arch_helpers.h>
|
|
|
|
#include <assert.h>
|
|
|
|
#include <platform_def.h>
|
|
|
|
#include <utils.h>
|
2017-05-19 09:59:37 +01:00
|
|
|
#include <xlat_tables_arch.h>
|
2016-06-30 15:11:07 +01:00
|
|
|
#include <xlat_tables.h>
|
|
|
|
#include "../xlat_tables_private.h"
|
|
|
|
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
#if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
|
2017-11-08 12:53:47 +00:00
|
|
|
#error ARMv7 target does not support LPAE MMU descriptors
|
|
|
|
#endif
|
|
|
|
|
2017-05-19 09:59:37 +01:00
|
|
|
#define XLAT_TABLE_LEVEL_BASE \
|
|
|
|
GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
|
2016-08-02 09:21:41 +01:00
|
|
|
|
2017-05-19 09:59:37 +01:00
|
|
|
#define NUM_BASE_LEVEL_ENTRIES \
|
|
|
|
GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
|
2016-06-30 15:11:07 +01:00
|
|
|
|
2016-08-02 09:21:41 +01:00
|
|
|
static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
|
|
|
|
__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
|
2016-06-30 15:11:07 +01:00
|
|
|
|
2017-03-22 15:48:51 +00:00
|
|
|
#if ENABLE_ASSERTIONS
|
2016-12-13 15:28:54 +00:00
|
|
|
static unsigned long long get_max_supported_pa(void)
|
|
|
|
{
|
|
|
|
/* Physical address space size for long descriptor format. */
|
|
|
|
return (1ULL << 40) - 1ULL;
|
|
|
|
}
|
2017-03-22 15:48:51 +00:00
|
|
|
#endif /* ENABLE_ASSERTIONS */
|
2016-12-13 15:28:54 +00:00
|
|
|
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
unsigned int xlat_arch_current_el(void)
|
Fix execute-never permissions in xlat tables libs
Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setting to 1 the XN bit in the Upper Attributes field in the translation
tables descriptors. Translation regimes that support two different
virtual address spaces (such as the one shared by EL1 and EL0) use bits
PXN and UXN instead.
The Trusted Firmware runs at EL3 and EL1, it has to handle translation
tables of both translation regimes, but the previous code handled both
regimes the same way, as if both had only 1 VA range.
When trying to set a descriptor as execute-never it would set the XN
bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is
at the same bit position as UXN, which means that EL0 was being
prevented from executing code at this region, not EL1 as the code
intended. Therefore, the PXN bit was unset to 0 all the time. The result
is that, in AArch64 mode, read-only data sections of BL2 weren't
protected from being executed.
This patch adds support of translation regimes with two virtual address
spaces to both versions of the translation tables library, fixing the
execute-never permissions for translation tables in EL1.
The library currently does not support initializing translation tables
for EL0 software, therefore it does not set/unset the UXN bit. If EL1
software needs to initialize translation tables for EL0 software, it
should use a different library instead.
Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-27 13:30:22 +01:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System,
|
|
|
|
* SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
|
|
|
|
*/
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
return 3U;
|
Fix execute-never permissions in xlat tables libs
Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setting to 1 the XN bit in the Upper Attributes field in the translation
tables descriptors. Translation regimes that support two different
virtual address spaces (such as the one shared by EL1 and EL0) use bits
PXN and UXN instead.
The Trusted Firmware runs at EL3 and EL1, it has to handle translation
tables of both translation regimes, but the previous code handled both
regimes the same way, as if both had only 1 VA range.
When trying to set a descriptor as execute-never it would set the XN
bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is
at the same bit position as UXN, which means that EL0 was being
prevented from executing code at this region, not EL1 as the code
intended. Therefore, the PXN bit was unset to 0 all the time. The result
is that, in AArch64 mode, read-only data sections of BL2 weren't
protected from being executed.
This patch adds support of translation regimes with two virtual address
spaces to both versions of the translation tables library, fixing the
execute-never permissions for translation tables in EL1.
The library currently does not support initializing translation tables
for EL0 software, therefore it does not set/unset the UXN bit. If EL1
software needs to initialize translation tables for EL0 software, it
should use a different library instead.
Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-27 13:30:22 +01:00
|
|
|
}
|
|
|
|
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
uint64_t xlat_arch_get_xn_desc(unsigned int el __unused)
|
Fix execute-never permissions in xlat tables libs
Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setting to 1 the XN bit in the Upper Attributes field in the translation
tables descriptors. Translation regimes that support two different
virtual address spaces (such as the one shared by EL1 and EL0) use bits
PXN and UXN instead.
The Trusted Firmware runs at EL3 and EL1, it has to handle translation
tables of both translation regimes, but the previous code handled both
regimes the same way, as if both had only 1 VA range.
When trying to set a descriptor as execute-never it would set the XN
bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is
at the same bit position as UXN, which means that EL0 was being
prevented from executing code at this region, not EL1 as the code
intended. Therefore, the PXN bit was unset to 0 all the time. The result
is that, in AArch64 mode, read-only data sections of BL2 weren't
protected from being executed.
This patch adds support of translation regimes with two virtual address
spaces to both versions of the translation tables library, fixing the
execute-never permissions for translation tables in EL1.
The library currently does not support initializing translation tables
for EL0 software, therefore it does not set/unset the UXN bit. If EL1
software needs to initialize translation tables for EL0 software, it
should use a different library instead.
Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-27 13:30:22 +01:00
|
|
|
{
|
|
|
|
return UPPER_ATTRS(XN);
|
|
|
|
}
|
|
|
|
|
2016-06-30 15:11:07 +01:00
|
|
|
void init_xlat_tables(void)
|
|
|
|
{
|
|
|
|
unsigned long long max_pa;
|
|
|
|
uintptr_t max_va;
|
|
|
|
print_mmap();
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
|
2016-08-02 09:21:41 +01:00
|
|
|
&max_va, &max_pa);
|
2016-12-13 15:28:54 +00:00
|
|
|
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
|
|
|
|
assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
|
|
|
|
assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
|
2016-06-30 15:11:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* Function for enabling the MMU in Secure PL1, assuming that the
|
|
|
|
* page-tables have already been created.
|
|
|
|
******************************************************************************/
|
2018-08-07 19:59:49 +01:00
|
|
|
#if !ERROR_DEPRECATED
|
2016-06-30 15:11:07 +01:00
|
|
|
void enable_mmu_secure(unsigned int flags)
|
2018-08-07 19:59:49 +01:00
|
|
|
{
|
|
|
|
enable_mmu_svc_mon(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
void enable_mmu_direct(unsigned int flags)
|
|
|
|
{
|
|
|
|
enable_mmu_direct_svc_mon(flags);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void enable_mmu_svc_mon(unsigned int flags)
|
2016-06-30 15:11:07 +01:00
|
|
|
{
|
|
|
|
unsigned int mair0, ttbcr, sctlr;
|
|
|
|
uint64_t ttbr0;
|
|
|
|
|
|
|
|
assert(IS_IN_SECURE());
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
assert((read_sctlr() & SCTLR_M_BIT) == 0U);
|
2016-06-30 15:11:07 +01:00
|
|
|
|
|
|
|
/* Set attributes in the right indices of the MAIR */
|
|
|
|
mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
|
|
|
|
mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
|
|
|
|
ATTR_IWBWA_OWBWA_NTR_INDEX);
|
|
|
|
mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
|
|
|
|
ATTR_NON_CACHEABLE_INDEX);
|
|
|
|
write_mair0(mair0);
|
|
|
|
|
|
|
|
/* Invalidate TLBs at the current exception level */
|
|
|
|
tlbiall();
|
|
|
|
|
|
|
|
/*
|
2017-03-16 17:16:34 +00:00
|
|
|
* Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
|
2016-06-30 15:11:07 +01:00
|
|
|
*/
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
int t0sz = 32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);
|
|
|
|
|
|
|
|
if ((flags & XLAT_TABLE_NC) != 0U) {
|
2017-03-16 17:16:34 +00:00
|
|
|
/* Inner & outer non-cacheable non-shareable. */
|
|
|
|
ttbcr = TTBCR_EAE_BIT |
|
|
|
|
TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
TTBCR_RGN0_INNER_NC | (uint32_t) t0sz;
|
2017-03-16 17:16:34 +00:00
|
|
|
} else {
|
|
|
|
/* Inner & outer WBWA & shareable. */
|
|
|
|
ttbcr = TTBCR_EAE_BIT |
|
|
|
|
TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
TTBCR_RGN0_INNER_WBA | (uint32_t) t0sz;
|
2017-03-16 17:16:34 +00:00
|
|
|
}
|
2016-06-30 15:11:07 +01:00
|
|
|
ttbcr |= TTBCR_EPD1_BIT;
|
|
|
|
write_ttbcr(ttbcr);
|
|
|
|
|
|
|
|
/* Set TTBR0 bits as well */
|
2016-08-02 09:21:41 +01:00
|
|
|
ttbr0 = (uintptr_t) base_xlation_table;
|
2016-06-30 15:11:07 +01:00
|
|
|
write64_ttbr0(ttbr0);
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
write64_ttbr1(0U);
|
2016-06-30 15:11:07 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure all translation table writes have drained
|
|
|
|
* into memory, the TLB invalidation is complete,
|
|
|
|
* and translation register writes are committed
|
|
|
|
* before enabling the MMU
|
|
|
|
*/
|
2017-06-20 09:25:10 +01:00
|
|
|
dsbish();
|
2016-06-30 15:11:07 +01:00
|
|
|
isb();
|
|
|
|
|
|
|
|
sctlr = read_sctlr();
|
|
|
|
sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
|
|
|
|
|
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 10:20:53 +01:00
|
|
|
if ((flags & DISABLE_DCACHE) != 0U)
|
2016-06-30 15:11:07 +01:00
|
|
|
sctlr &= ~SCTLR_C_BIT;
|
|
|
|
else
|
|
|
|
sctlr |= SCTLR_C_BIT;
|
|
|
|
|
|
|
|
write_sctlr(sctlr);
|
|
|
|
|
|
|
|
/* Ensure the MMU enable takes effect immediately */
|
|
|
|
isb();
|
|
|
|
}
|
2018-04-27 15:06:57 +01:00
|
|
|
|
2018-08-07 19:59:49 +01:00
|
|
|
void enable_mmu_direct_svc_mon(unsigned int flags)
|
2018-04-27 15:06:57 +01:00
|
|
|
{
|
2018-08-07 19:59:49 +01:00
|
|
|
enable_mmu_svc_mon(flags);
|
2018-04-27 15:06:57 +01:00
|
|
|
}
|