2016-10-14 02:13:34 +01:00
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <board_def.h>
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#include <common_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stack */
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#if IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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2016-10-18 20:32:06 +01:00
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
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K3_CLUSTER1_CORE_COUNT + \
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K3_CLUSTER2_CORE_COUNT + \
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K3_CLUSTER3_CORE_COUNT)
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#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \
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(K3_CLUSTER1_MSMC_PORT != UNUSED) + \
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(K3_CLUSTER2_MSMC_PORT != UNUSED) + \
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(K3_CLUSTER3_MSMC_PORT != UNUSED))
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#define UNUSED -1
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#if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT)
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#define K3_CLUSTER1_CORE_COUNT 0
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#define K3_CLUSTER1_MSMC_PORT UNUSED
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#endif
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#if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT)
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#define K3_CLUSTER2_CORE_COUNT 0
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#define K3_CLUSTER2_MSMC_PORT UNUSED
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#endif
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#if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT)
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#define K3_CLUSTER3_CORE_COUNT 0
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#define K3_CLUSTER3_MSMC_PORT UNUSED
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#endif
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#if K3_CLUSTER0_MSMC_PORT == UNUSED
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#error "ARM cluster 0 must be used"
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#endif
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#if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \
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((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \
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((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0))
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#error "Unused ports must have 0 ARM cores"
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#endif
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#define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT
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2016-10-14 02:13:34 +01:00
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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/*******************************************************************************
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* Memory layout constants
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******************************************************************************/
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/*
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* ARM-TF lives in SRAM, partition it here
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*/
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#define SHARED_RAM_BASE BL31_LIMIT
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#define SHARED_RAM_SIZE 0x00001000
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/*
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* BL3-1 specific defines.
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*
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* Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM.
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*/
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#define BL31_BASE SEC_SRAM_BASE
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#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL31_LIMIT
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2016-10-14 02:13:45 +01:00
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/*
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* Defines the maximum number of translation tables that are allocated by the
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* translation table library code. To minimize the amount of runtime memory
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* used, choose the smallest value needed to map the required virtual addresses
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* for each BL stage.
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*/
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#define MAX_XLAT_TABLES 8
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/*
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* Defines the maximum number of regions that are allocated by the translation
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* table library code. A region consists of physical base address, virtual base
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* address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
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* defined in the `mmap_region_t` structure. The platform defines the regions
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* that should be mapped. Then, the translation table library will create the
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* corresponding tables and descriptors at runtime. To minimize the amount of
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* runtime memory used, choose the smallest value needed to register the
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* required regions for each BL stage.
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*/
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#define MAX_MMAP_REGIONS 8
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/*
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* Defines the total size of the address space in bytes. For example, for a 32
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* bit address space, this value should be `(1ull << 32)`.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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2016-10-14 02:13:34 +01:00
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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