2013-10-25 09:08:21 +01:00
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/*
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2017-06-05 22:54:46 +01:00
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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2013-10-25 09:08:21 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2013-10-25 09:08:21 +01:00
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*/
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2014-08-14 12:49:05 +01:00
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#ifndef __CORTEX_A53_H__
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#define __CORTEX_A53_H__
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2013-10-25 09:08:21 +01:00
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2014-08-14 12:49:05 +01:00
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/* Cortex-A53 midr for revision 0 */
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2017-05-26 02:04:48 +01:00
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#define CORTEX_A53_MIDR U(0x410FD030)
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2013-10-25 09:08:21 +01:00
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2015-08-21 11:22:51 +01:00
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/* Retention timer tick definitions */
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2017-05-26 02:04:48 +01:00
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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2015-08-21 11:22:51 +01:00
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2014-08-14 12:49:05 +01:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
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2014-08-14 13:36:41 +01:00
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
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2013-10-25 09:08:21 +01:00
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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2015-08-21 11:22:51 +01:00
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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2015-08-21 11:22:51 +01:00
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2016-07-01 08:22:41 +01:00
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
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2016-07-01 08:22:41 +01:00
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2015-07-29 13:55:31 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
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2015-07-29 13:55:31 +01:00
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
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2015-07-29 13:55:31 +01:00
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
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2015-07-29 13:55:31 +01:00
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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2015-08-21 11:22:51 +01:00
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
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2015-08-21 11:22:51 +01:00
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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2015-08-21 11:22:51 +01:00
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2016-07-01 08:22:41 +01:00
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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2017-08-09 16:42:40 +01:00
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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2014-08-14 12:49:05 +01:00
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#endif /* __CORTEX_A53_H__ */
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