2018-09-23 08:36:52 +01:00
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/*
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2019-06-14 00:41:10 +01:00
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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2018-09-23 08:36:52 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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2018-12-14 00:18:21 +00:00
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#include <common/debug.h>
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2018-09-23 08:36:52 +01:00
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#include "../qos_common.h"
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2019-06-14 00:41:10 +01:00
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#include "../qos_reg.h"
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2018-09-23 08:36:52 +01:00
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#include "qos_init_m3_v10.h"
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#define RCAR_QOS_VERSION "rev.0.19"
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2019-06-14 00:44:43 +01:00
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#include "qos_init_m3_v10_mstat.h"
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2018-09-23 08:36:52 +01:00
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2019-06-14 15:08:19 +01:00
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struct rcar_gen3_dbsc_qos_settings m3_v10_qos[] = {
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2018-09-23 08:36:52 +01:00
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/* BUFCAM settings */
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/* DBSC_DBCAM0CNF0 not set */
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2019-06-14 15:08:19 +01:00
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{ DBSC_DBCAM0CNF1, 0x00043218 },
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{ DBSC_DBCAM0CNF2, 0x000000F4 },
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{ DBSC_DBCAM0CNF3, 0x00000000 },
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{ DBSC_DBSCHCNT0, 0x080F0037 },
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2018-09-23 08:36:52 +01:00
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/* DBSC_DBSCHCNT1 not set */
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2019-06-14 15:08:19 +01:00
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{ DBSC_DBSCHSZ0, 0x00000001 },
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{ DBSC_DBSCHRW0, 0x22421111 },
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2018-09-23 08:36:52 +01:00
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2019-06-14 00:51:40 +01:00
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/* DDR3 */
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2019-06-14 15:08:19 +01:00
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{ DBSC_SCFCTST2, 0x012F1123 },
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2018-09-23 08:36:52 +01:00
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/* QoS Settings */
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2019-06-14 15:08:19 +01:00
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{ DBSC_DBSCHQOS00, 0x00000F00 },
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{ DBSC_DBSCHQOS01, 0x00000B00 },
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{ DBSC_DBSCHQOS02, 0x00000000 },
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{ DBSC_DBSCHQOS03, 0x00000000 },
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{ DBSC_DBSCHQOS40, 0x00000300 },
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{ DBSC_DBSCHQOS41, 0x000002F0 },
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{ DBSC_DBSCHQOS42, 0x00000200 },
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{ DBSC_DBSCHQOS43, 0x00000100 },
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{ DBSC_DBSCHQOS90, 0x00000300 },
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{ DBSC_DBSCHQOS91, 0x000002F0 },
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{ DBSC_DBSCHQOS92, 0x00000200 },
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{ DBSC_DBSCHQOS93, 0x00000100 },
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{ DBSC_DBSCHQOS130, 0x00000100 },
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{ DBSC_DBSCHQOS131, 0x000000F0 },
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{ DBSC_DBSCHQOS132, 0x000000A0 },
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{ DBSC_DBSCHQOS133, 0x00000040 },
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{ DBSC_DBSCHQOS140, 0x000000C0 },
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{ DBSC_DBSCHQOS141, 0x000000B0 },
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{ DBSC_DBSCHQOS142, 0x00000080 },
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{ DBSC_DBSCHQOS143, 0x00000040 },
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{ DBSC_DBSCHQOS150, 0x00000040 },
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{ DBSC_DBSCHQOS151, 0x00000030 },
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{ DBSC_DBSCHQOS152, 0x00000020 },
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{ DBSC_DBSCHQOS153, 0x00000010 },
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};
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2018-09-23 08:36:52 +01:00
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void qos_init_m3_v10(void)
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{
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2019-06-14 15:08:19 +01:00
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rcar_qos_dbsc_setting(m3_v10_qos, ARRAY_SIZE(m3_v10_qos), false);
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2018-09-23 08:36:52 +01:00
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/* DRAM Split Address mapping */
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#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
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#if RCAR_LSI == RCAR_M3
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#error "Don't set DRAM Split 4ch(M3)"
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#else
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ERROR("DRAM Split 4ch not supported.(M3)");
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panic();
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#endif
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#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
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(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
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NOTICE("BL2: DRAM Split is 2ch\n");
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io_write_32(AXI_ADSPLCR0, 0x00000000U);
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io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
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| ADSPLCR0_SPLITSEL(0xFFU)
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| ADSPLCR0_AREA(0x1CU)
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| ADSPLCR0_SWP);
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io_write_32(AXI_ADSPLCR2, 0x089A0000U);
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io_write_32(AXI_ADSPLCR3, 0x00000000U);
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#else
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NOTICE("BL2: DRAM Split is OFF\n");
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#endif
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#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
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#endif
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/* Resource Alloc setting */
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2019-06-14 00:41:10 +01:00
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io_write_32(QOSCTRL_RAS, 0x00000028U);
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io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
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io_write_32(QOSCTRL_REGGD, 0x00000000U);
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io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
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io_write_32(QOSCTRL_DANT, 0x00100804U);
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io_write_32(QOSCTRL_EC, 0x00000000U);
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io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
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io_write_32(QOSCTRL_FSS, 0x000003e8U);
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io_write_32(QOSCTRL_INSFC, 0xC7840001U);
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io_write_32(QOSCTRL_BERR, 0x00000000U);
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io_write_32(QOSCTRL_RACNT0, 0x00000000U);
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2018-09-23 08:36:52 +01:00
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2019-06-14 00:41:10 +01:00
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/* QOSBW setting */
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io_write_32(QOSCTRL_SL_INIT,
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2018-09-23 08:36:52 +01:00
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SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
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2019-06-14 00:41:10 +01:00
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io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
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2018-09-23 08:36:52 +01:00
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2019-06-14 00:41:10 +01:00
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/* QOSBW SRAM setting */
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2019-06-14 00:39:27 +01:00
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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2018-09-23 08:36:52 +01:00
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}
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/* 3DG bus Leaf setting */
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io_write_32(0xFD820808U, 0x00001234U);
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io_write_32(0xFD820800U, 0x00000006U);
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io_write_32(0xFD821800U, 0x00000006U);
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io_write_32(0xFD822800U, 0x00000006U);
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io_write_32(0xFD823800U, 0x00000006U);
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io_write_32(0xFD824800U, 0x00000006U);
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io_write_32(0xFD825800U, 0x00000006U);
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io_write_32(0xFD826800U, 0x00000006U);
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io_write_32(0xFD827800U, 0x00000006U);
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/* RT bus Leaf setting */
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io_write_32(0xFFC50800U, 0x00000000U);
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io_write_32(0xFFC51800U, 0x00000000U);
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/* Resource Alloc start */
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2019-06-14 00:41:10 +01:00
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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2018-09-23 08:36:52 +01:00
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2019-06-14 00:41:10 +01:00
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/* QOSBW start */
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io_write_32(QOSCTRL_STATQC, 0x00000001U);
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2018-09-23 08:36:52 +01:00
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#else
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NOTICE("BL2: QoS is None\n");
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/* Resource Alloc setting */
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2019-06-14 00:41:10 +01:00
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io_write_32(QOSCTRL_EC, 0x00000000U);
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2018-09-23 08:36:52 +01:00
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/* Resource Alloc start */
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2019-06-14 00:41:10 +01:00
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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2018-09-23 08:36:52 +01:00
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#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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}
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