Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration
* changes: fix(errata): workaround for Neoverse V1 erratum 2216392 fix(errata): workaround for Cortex A78 erratum 2242635 fix(errata): workaround for Neoverse-N2 erratum 2280757 fix(errata): workaround for Neoverse-N2 erratum 2242400 fix(errata): workaround for Neoverse-N2 erratum 2138958 fix(errata): workaround for Neoverse-N2 erratum 2242415
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
0b5e33c7aa
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@ -288,6 +288,10 @@ For Cortex-A78, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
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is still open.
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- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
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CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
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is present in r0p0 but there is no workaround. It is still open.
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For Cortex-A78 AE, the following errata build flags are defined :
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- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
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@ -340,11 +344,6 @@ For Neoverse N1, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
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revisions r0p0, r1p0, and r2p0 there is no workaround.
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For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
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For Neoverse V1, the following errata build flags are defined :
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- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
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@ -379,6 +378,11 @@ For Neoverse V1, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
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It is still open.
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- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
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CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
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issue is present in r0p0 as well but there is no workaround for that
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revision. It is still open.
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For Cortex-A710, the following errata build flags are defined :
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- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
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@ -407,6 +411,9 @@ For Cortex-A710, the following errata build flags are defined :
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For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
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- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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@ -422,6 +429,18 @@ For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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DSU Errata Workarounds
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----------------------
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@ -28,6 +28,7 @@
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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@ -40,6 +41,8 @@
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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@ -227,6 +227,42 @@ func check_errata_2132060
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b cpu_rev_var_ls
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endfunc check_errata_2132060
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/* --------------------------------------------------------------------
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* Errata Workaround for A78 Erratum 2242635.
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* This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
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* processor and is still open.
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* The issue also exists in r0p0 but there is no fix in that revision.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------------------------
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*/
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func errata_a78_2242635_wa
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/* Compare x0 against revisions r1p0 - r1p2 */
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mov x17, x30
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bl check_errata_2242635
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cbz x0, 1f
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ldr x0, =0x5
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msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
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ldr x0, =0x10F600E000
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msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
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ldr x0, =0x10FF80E000
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msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
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ldr x0, =0x80000000003FF
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msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
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isb
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1:
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ret x17
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endfunc errata_a78_2242635_wa
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func check_errata_2242635
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/* Applies to revisions r1p0 through r1p2. */
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mov x1, #CPU_REV(1, 0)
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mov x2, #CPU_REV(1, 2)
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b cpu_rev_var_range
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endfunc check_errata_2242635
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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@ -266,6 +302,11 @@ func cortex_a78_reset_func
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bl errata_a78_2132060_wa
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#endif
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#if ERRATA_A78_2242635
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mov x0, x18
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bl errata_a78_2242635_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -326,6 +367,7 @@ func cortex_a78_errata_report
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report_errata ERRATA_A78_1821534, cortex_a78, 1821534
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report_errata ERRATA_A78_1952683, cortex_a78, 1952683
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report_errata ERRATA_A78_2132060, cortex_a78, 2132060
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report_errata ERRATA_A78_2242635, cortex_a78, 2242635
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ldp x8, x30, [sp], #16
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ret
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@ -183,6 +183,34 @@ func check_errata_2138956
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b cpu_rev_var_ls
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endfunc check_errata_2138956
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2242415.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_n2_2242415_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2242415
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cbz x0, 1f
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/* Apply instruction patching sequence */
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mrs x1, NEOVERSE_N2_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
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msr NEOVERSE_N2_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2242415_wa
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func check_errata_2242415
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2242415
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2138953.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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@ -212,6 +240,99 @@ func check_errata_2138953
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b cpu_rev_var_ls
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endfunc check_errata_2138953
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2138958.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_n2_2138958_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2138958
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cbz x0, 1f
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/* Apply instruction patching sequence */
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mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
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orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
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msr NEOVERSE_N2_CPUACTLR5_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2138958_wa
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func check_errata_2138958
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2138958
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2242400.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_n2_2242400_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2242400
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cbz x0, 1f
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/* Apply instruction patching sequence */
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mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
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orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
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msr NEOVERSE_N2_CPUACTLR5_EL1, x1
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ldr x0, =0x2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10F600E000
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FF80E000
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x80000000003FF
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msr S3_6_c15_c8_1, x0
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isb
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1:
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ret x17
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endfunc errata_n2_2242400_wa
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func check_errata_2242400
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2242400
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2280757.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_n2_2280757_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2280757
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cbz x0, 1f
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/* Apply instruction patching sequence */
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mrs x1, NEOVERSE_N2_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
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msr NEOVERSE_N2_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2280757_wa
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func check_errata_2280757
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2280757
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/* -------------------------------------------
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* The CPU Ops reset function for Neoverse N2.
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* -------------------------------------------
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@ -238,13 +359,13 @@ func neoverse_n2_reset_func
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#endif
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#if ERRATA_N2_2025414
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mov x0, x18
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bl errata_n2_2025414_wa
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mov x0, x18
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bl errata_n2_2025414_wa
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#endif
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#if ERRATA_N2_2189731
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mov x0, x18
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bl errata_n2_2189731_wa
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mov x0, x18
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bl errata_n2_2189731_wa
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#endif
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@ -258,6 +379,26 @@ func neoverse_n2_reset_func
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bl errata_n2_2138953_wa
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#endif
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#if ERRATA_N2_2242415
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mov x0, x18
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bl errata_n2_2242415_wa
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#endif
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#if ERRATA_N2_2138958
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mov x0, x18
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bl errata_n2_2138958_wa
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#endif
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#if ERRATA_N2_2242400
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mov x0, x18
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bl errata_n2_2242400_wa
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#endif
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#if ERRATA_N2_2280757
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mov x0, x18
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bl errata_n2_2280757_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
|
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mrs x0, cptr_el3
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@ -324,6 +465,10 @@ func neoverse_n2_errata_report
|
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report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
|
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report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
|
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report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
|
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report_errata ERRATA_N2_2242415, neoverse_n2, 2242415
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report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
|
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report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
|
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report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
|
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ldp x8, x30, [sp], #16
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ret
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|
|
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@ -288,6 +288,43 @@ func check_errata_2108267
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b cpu_rev_var_ls
|
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endfunc check_errata_2108267
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|
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/* --------------------------------------------------
|
||||
* Errata Workaround for Neoverse V1 Errata #2216392.
|
||||
* This applies to revisions r1p0 and r1p1 and is
|
||||
* still open.
|
||||
* This issue is also present in r0p0 but there is no
|
||||
* workaround in that revision.
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* --------------------------------------------------
|
||||
*/
|
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func errata_neoverse_v1_2216392_wa
|
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/* Check workaround compatibility. */
|
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mov x17, x30
|
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bl check_errata_2216392
|
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cbz x0, 1f
|
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|
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ldr x0, =0x5
|
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msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
|
||||
ldr x0, =0x10F600E000
|
||||
msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
|
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ldr x0, =0x10FF80E000
|
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msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
|
||||
ldr x0, =0x80000000003FF
|
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msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
|
||||
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_neoverse_v1_2216392_wa
|
||||
|
||||
func check_errata_2216392
|
||||
/* Applies to revisions r1p0 and r1p1. */
|
||||
mov x1, #CPU_REV(1, 0)
|
||||
mov x2, #CPU_REV(1, 1)
|
||||
b cpu_rev_var_range
|
||||
endfunc check_errata_2216392
|
||||
|
||||
/* ---------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ---------------------------------------------
|
||||
|
|
@ -326,6 +363,7 @@ func neoverse_v1_errata_report
|
|||
report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
|
||||
report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
|
||||
report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
|
||||
report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
|
|
@ -379,6 +417,11 @@ func neoverse_v1_reset_func
|
|||
bl errata_neoverse_v1_2108267_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_V1_2216392
|
||||
mov x0, x18
|
||||
bl errata_neoverse_v1_2216392_wa
|
||||
#endif
|
||||
|
||||
ret x19
|
||||
endfunc neoverse_v1_reset_func
|
||||
|
||||
|
|
|
|||
|
|
@ -311,6 +311,23 @@ ERRATA_A78_1941498 ?=0
|
|||
# well but there is no workaround for that revision.
|
||||
ERRATA_A78_1951500 ?=0
|
||||
|
||||
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
|
||||
# to revisions r0p0 and r1p0 of the A78 cpu.
|
||||
ERRATA_A78_1821534 ?=0
|
||||
|
||||
# Flag to apply erratum 1952683 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
|
||||
ERRATA_A78_1952683 ?=0
|
||||
|
||||
# Flag to apply erratum 2132060 workaround during reset. This erratum applies
|
||||
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
|
||||
ERRATA_A78_2132060 ?=0
|
||||
|
||||
# Flag to apply erratum 2242635 workaround during reset. This erratum applies
|
||||
# to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is
|
||||
# present in r0p0 as well but there is no workaround for that revision.
|
||||
ERRATA_A78_2242635 ?=0
|
||||
|
||||
# Flag to apply erratum 1941500 workaround during reset. This erratum applies
|
||||
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
|
||||
ERRATA_A78_AE_1941500 ?=0
|
||||
|
|
@ -319,18 +336,6 @@ ERRATA_A78_AE_1941500 ?=0
|
|||
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
|
||||
ERRATA_A78_AE_1951502 ?=0
|
||||
|
||||
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
|
||||
# to revisions r0p0 and r1p0 of the A78 cpu.
|
||||
ERRATA_A78_1821534 ?=0
|
||||
|
||||
# Flag to apply erratum 1952683 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
|
||||
ERRATA_A78_1952683 ?=0
|
||||
|
||||
# Flag to apply erratum 2132060 workaround during reset. This erratum applies
|
||||
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
|
||||
ERRATA_A78_2132060 ?=0
|
||||
|
||||
# Flag to apply T32 CLREX workaround during reset. This erratum applies
|
||||
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
|
||||
ERRATA_N1_1043202 ?=0
|
||||
|
|
@ -425,6 +430,11 @@ ERRATA_V1_2139242 ?=0
|
|||
# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
|
||||
ERRATA_V1_2108267 ?=0
|
||||
|
||||
# Flag to apply erratum 2216392 workaround during reset. This erratum applies
|
||||
# to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This
|
||||
# issue exists in r0p0 as well but there is no workaround for that revision.
|
||||
ERRATA_V1_2216392 ?=0
|
||||
|
||||
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
|
||||
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
|
||||
ERRATA_A710_1987031 ?=0
|
||||
|
|
@ -461,6 +471,22 @@ ERRATA_N2_2138956 ?=0
|
|||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2138953 ?=0
|
||||
|
||||
# Flag to apply erratum 2242415 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2242415 ?=0
|
||||
|
||||
# Flag to apply erratum 2138958 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2138958 ?=0
|
||||
|
||||
# Flag to apply erratum 2242400 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2242400 ?=0
|
||||
|
||||
# Flag to apply erratum 2280757 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2280757 ?=0
|
||||
|
||||
# Flag to apply erratum 2055002 workaround during reset. This erratum applies
|
||||
# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
|
||||
ERRATA_A710_2055002 ?=0
|
||||
|
|
@ -714,14 +740,6 @@ $(eval $(call add_define,ERRATA_A78_1941498))
|
|||
$(eval $(call assert_boolean,ERRATA_A78_1951500))
|
||||
$(eval $(call add_define,ERRATA_A78_1951500))
|
||||
|
||||
# Process ERRATA_A78_AE_1941500 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
|
||||
$(eval $(call add_define,ERRATA_A78_AE_1941500))
|
||||
|
||||
# Process ERRATA_A78_AE_1951502 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
|
||||
$(eval $(call add_define,ERRATA_A78_AE_1951502))
|
||||
|
||||
# Process ERRATA_A78_1821534 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A78_1821534))
|
||||
$(eval $(call add_define,ERRATA_A78_1821534))
|
||||
|
|
@ -734,6 +752,18 @@ $(eval $(call add_define,ERRATA_A78_1952683))
|
|||
$(eval $(call assert_boolean,ERRATA_A78_2132060))
|
||||
$(eval $(call add_define,ERRATA_A78_2132060))
|
||||
|
||||
# Process ERRATA_A78_2242635 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A78_2242635))
|
||||
$(eval $(call add_define,ERRATA_A78_2242635))
|
||||
|
||||
# Process ERRATA_A78_AE_1941500 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
|
||||
$(eval $(call add_define,ERRATA_A78_AE_1941500))
|
||||
|
||||
# Process ERRATA_A78_AE_1951502 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
|
||||
$(eval $(call add_define,ERRATA_A78_AE_1951502))
|
||||
|
||||
# Process ERRATA_N1_1043202 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N1_1043202))
|
||||
$(eval $(call add_define,ERRATA_N1_1043202))
|
||||
|
|
@ -826,6 +856,10 @@ $(eval $(call add_define,ERRATA_V1_2139242))
|
|||
$(eval $(call assert_boolean,ERRATA_V1_2108267))
|
||||
$(eval $(call add_define,ERRATA_V1_2108267))
|
||||
|
||||
# Process ERRATA_V1_2216392 flag
|
||||
$(eval $(call assert_boolean,ERRATA_V1_2216392))
|
||||
$(eval $(call add_define,ERRATA_V1_2216392))
|
||||
|
||||
# Process ERRATA_A710_1987031 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A710_1987031))
|
||||
$(eval $(call add_define,ERRATA_A710_1987031))
|
||||
|
|
@ -862,6 +896,22 @@ $(eval $(call add_define,ERRATA_N2_2138956))
|
|||
$(eval $(call assert_boolean,ERRATA_N2_2138953))
|
||||
$(eval $(call add_define,ERRATA_N2_2138953))
|
||||
|
||||
# Process ERRATA_N2_2242415 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2242415))
|
||||
$(eval $(call add_define,ERRATA_N2_2242415))
|
||||
|
||||
# Process ERRATA_N2_2138958 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2138958))
|
||||
$(eval $(call add_define,ERRATA_N2_2138958))
|
||||
|
||||
# Process ERRATA_N2_2242400 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2242400))
|
||||
$(eval $(call add_define,ERRATA_N2_2242400))
|
||||
|
||||
# Process ERRATA_N2_2280757 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2280757))
|
||||
$(eval $(call add_define,ERRATA_N2_2280757))
|
||||
|
||||
# Process ERRATA_A710_2055002 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A710_2055002))
|
||||
$(eval $(call add_define,ERRATA_A710_2055002))
|
||||
|
|
|
|||
Loading…
Reference in New Issue