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Merge changes I75f6d135,I4add470e,I0ecd3a2b,I67a63d73 into integration 

* changes:
  board/rddaniel: intialize tzc400 controllers
  plat/arm/tzc: add support to configure multiple tzc400
  plat/arm: allow boards to specify second DRAM Base address
  plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS
This commit is contained in:
Manish Pandey 2020-02-28 16:52:55 +00:00 committed by TrustedFirmware Code Review
parent 351d358fed 4bbb3a5416
commit 2403813779
12 changed files with 53 additions and 22 deletions
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9
include/plat/arm/board/common/board_css_def.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -50,13 +50,6 @@
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
/*
* Required platform porting definitions common to all ARM CSS-based
* development platforms
*/
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
/* UART related constants */ /* UART related constants */
#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ

3
include/plat/arm/common/plat_arm.h
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@ -152,7 +152,8 @@ void arm_setup_romlib(void);
int arm_io_setup(void); int arm_io_setup(void);
/* Security utility functions */ /* Security utility functions */
void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); void arm_tzc400_setup(uintptr_t tzc_base,
const arm_tzc_regions_info_t *tzc_regions);
struct tzc_dmc500_driver_data; struct tzc_dmc500_driver_data;
void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
const arm_tzc_regions_info_t *tzc_regions); const arm_tzc_regions_info_t *tzc_regions);

3
include/plat/arm/css/common/css_def.h
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@ -189,9 +189,6 @@
/* Load address of Non-Secure Image for CSS platform ports */ /* Load address of Non-Secure Image for CSS platform ports */
#define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) #define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000)
/* TZC related constants */
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
/* /*
* Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
* command * command

4
plat/arm/board/fvp/fvp_security.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -22,5 +22,5 @@ void plat_arm_security_setup(void)
*/ */
if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U) if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
arm_tzc400_setup(NULL); arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
} }

6
plat/arm/board/juno/include/platform_def.h
View File

@ -50,6 +50,9 @@
#define NSRAM_BASE UL(0x2e000000) #define NSRAM_BASE UL(0x2e000000)
#define NSRAM_SIZE UL(0x00008000) /* 32KB */ #define NSRAM_SIZE UL(0x00008000) /* 32KB */
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
/* virtual address used by dynamic mem_protect for chunk_base */ /* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
@ -212,6 +215,9 @@
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
/* TZC related constants */
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
/* /*
* Required ARM CSS based platform porting definitions * Required ARM CSS based platform porting definitions
*/ */

6
plat/arm/board/juno/juno_security.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -127,13 +127,13 @@ void plat_arm_security_setup(void)
init_debug_cfg(); init_debug_cfg();
/* Initialize the TrustZone Controller */ /* Initialize the TrustZone Controller */
#ifdef JUNO_TZMP1 #ifdef JUNO_TZMP1
arm_tzc400_setup(juno_tzmp1_tzc_regions); arm_tzc400_setup(PLAT_ARM_TZC_BASE, juno_tzmp1_tzc_regions);
INFO("TZC protected shared memory base address for TZMP usecase: %p\n", INFO("TZC protected shared memory base address for TZMP usecase: %p\n",
(void *)JUNO_AP_TZC_SHARE_DRAM1_BASE); (void *)JUNO_AP_TZC_SHARE_DRAM1_BASE);
INFO("TZC protected shared memory end address for TZMP usecase: %p\n", INFO("TZC protected shared memory end address for TZMP usecase: %p\n",
(void *)JUNO_AP_TZC_SHARE_DRAM1_END); (void *)JUNO_AP_TZC_SHARE_DRAM1_END);
#else #else
arm_tzc400_setup(NULL); arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
#endif #endif
/* Do ARM CSS internal NIC setup */ /* Do ARM CSS internal NIC setup */
css_init_nic400(); css_init_nic400();

15
plat/arm/board/rddaniel/include/platform_def.h
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@ -21,6 +21,21 @@
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC400_OFFSET UL(0x1000000)
#define TZC400_COUNT 4
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
(n * TZC400_OFFSET))
#define TZC_NSAID_ALL_AP U(0)
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP))
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */

2
plat/arm/board/rddaniel/platform.mk
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@ -18,6 +18,8 @@ BL2_SOURCES += ${RDDANIEL_BASE}/rddaniel_plat.c \
${RDDANIEL_BASE}/rddaniel_security.c \ ${RDDANIEL_BASE}/rddaniel_security.c \
${RDDANIEL_BASE}/rddaniel_err.c \ ${RDDANIEL_BASE}/rddaniel_err.c \
lib/utils/mem_region.c \ lib/utils/mem_region.c \
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \ BL31_SOURCES += ${SGI_CPU_SOURCES} \

10
plat/arm/board/rddaniel/rddaniel_security.c
View File

@ -4,9 +4,19 @@
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h> #include <platform_def.h>
static const arm_tzc_regions_info_t tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
{}
};
/* Initialize the secure environment */ /* Initialize the secure environment */
void plat_arm_security_setup(void) void plat_arm_security_setup(void)
{ {
int i;
for (i = 0; i < TZC400_COUNT; i++)
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
} }

5
plat/arm/board/sgm775/include/platform_def.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -12,6 +12,9 @@
#define PLAT_MAX_CPUS_PER_CLUSTER U(8) #define PLAT_MAX_CPUS_PER_CLUSTER U(8)
#define PLAT_MAX_PE_PER_CPU U(1) #define PLAT_MAX_PE_PER_CPU U(1)
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */

9
plat/arm/common/arm_tzc400.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -19,7 +19,8 @@
* When booting an EL3 payload, this is simplified: we configure region 0 with * When booting an EL3 payload, this is simplified: we configure region 0 with
* secure access only and do not enable any other region. * secure access only and do not enable any other region.
******************************************************************************/ ******************************************************************************/
void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions) void arm_tzc400_setup(uintptr_t tzc_base,
const arm_tzc_regions_info_t *tzc_regions)
{ {
#ifndef EL3_PAYLOAD_BASE #ifndef EL3_PAYLOAD_BASE
unsigned int region_index = 1U; unsigned int region_index = 1U;
@ -32,7 +33,7 @@ void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
INFO("Configuring TrustZone Controller\n"); INFO("Configuring TrustZone Controller\n");
tzc400_init(PLAT_ARM_TZC_BASE); tzc400_init(tzc_base);
/* Disable filters. */ /* Disable filters. */
tzc400_disable_filters(); tzc400_disable_filters();
@ -74,5 +75,5 @@ void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
void plat_arm_security_setup(void) void plat_arm_security_setup(void)
{ {
arm_tzc400_setup(NULL); arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
} }

3
plat/arm/css/sgi/include/sgi_base_platform_def.h
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@ -123,6 +123,9 @@
#define PLAT_ARM_NSRAM_BASE 0x06000000 #define PLAT_ARM_NSRAM_BASE 0x06000000
#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)