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Rename Neoverse Zeus to Neoverse V1 

Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
This commit is contained in:
Jimmy Brisson 2020-09-30 15:28:03 -05:00 committed by Madhukar Pappireddy
parent 5effe0beba
commit 467937b63d
6 changed files with 36 additions and 36 deletions
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16
include/lib/cpus/aarch64/neoverse_zeus.h → include/lib/cpus/aarch64/neoverse_v1.h
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@ -1,23 +1,23 @@
/* /*
* Copyright (c) 2019, ARM Limited. All rights reserved. * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef NEOVERSE_ZEUS_H #ifndef NEOVERSE_V1_H
#define NEOVERSE_ZEUS_H #define NEOVERSE_V1_H
#define NEOVERSE_ZEUS_MIDR U(0x410FD400) #define NEOVERSE_V1_MIDR U(0x410FD400)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions. * CPU Extended Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions * CPU Power Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* NEOVERSE_ZEUS_H */ #endif /* NEOVERSE_V1_H */

48
lib/cpus/aarch64/neoverse_zeus.S → lib/cpus/aarch64/neoverse_v1.S
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, ARM Limited. All rights reserved. * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,46 +7,46 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <neoverse_zeus.h> #include <neoverse_v1.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
/* Hardware handled coherency */ /* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0 #if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* 64-bit only core */ /* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1 #if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
/* --------------------------------------------- /* ---------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* --------------------------------------------- * ---------------------------------------------
*/ */
func neoverse_zeus_core_pwr_dwn func neoverse_v1_core_pwr_dwn
/* --------------------------------------------- /* ---------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc neoverse_zeus_core_pwr_dwn endfunc neoverse_v1_core_pwr_dwn
/* /*
* Errata printing function for Neoverse Zeus. Must follow AAPCS. * Errata printing function for Neoverse V1. Must follow AAPCS.
*/ */
#if REPORT_ERRATA #if REPORT_ERRATA
func neoverse_zeus_errata_report func neoverse_v1_errata_report
ret ret
endfunc neoverse_zeus_errata_report endfunc neoverse_v1_errata_report
#endif #endif
func neoverse_zeus_reset_func func neoverse_v1_reset_func
mov x19, x30 mov x19, x30
/* Disable speculative loads */ /* Disable speculative loads */
@ -54,10 +54,10 @@ func neoverse_zeus_reset_func
isb isb
ret x19 ret x19
endfunc neoverse_zeus_reset_func endfunc neoverse_v1_reset_func
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Neoverse-Zeus specific * This function provides Neoverse-V1 specific
* register information for crash reporting. * register information for crash reporting.
* It needs to return with x6 pointing to * It needs to return with x6 pointing to
* a list of register names in ascii and * a list of register names in ascii and
@ -65,16 +65,16 @@ endfunc neoverse_zeus_reset_func
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.neoverse_zeus_regs, "aS" .section .rodata.neoverse_v1_regs, "aS"
neoverse_zeus_regs: /* The ascii list of register names to be reported */ neoverse_v1_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func neoverse_zeus_cpu_reg_dump func neoverse_v1_cpu_reg_dump
adr x6, neoverse_zeus_regs adr x6, neoverse_v1_regs
mrs x8, NEOVERSE_ZEUS_CPUECTLR_EL1 mrs x8, NEOVERSE_V1_CPUECTLR_EL1
ret ret
endfunc neoverse_zeus_cpu_reg_dump endfunc neoverse_v1_cpu_reg_dump
declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \ declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
neoverse_zeus_reset_func, \ neoverse_v1_reset_func, \
neoverse_zeus_core_pwr_dwn neoverse_v1_core_pwr_dwn

2
plat/arm/board/arm_fpga/platform.mk
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@ -61,7 +61,7 @@ else
lib/cpus/aarch64/cortex_a78.S \ lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_zeus.S \ lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_a65ae.S \

2
plat/arm/board/fvp/platform.mk
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@ -120,7 +120,7 @@ else
lib/cpus/aarch64/cortex_a78.S \ lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_zeus.S \ lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_klein.S \ lib/cpus/aarch64/cortex_klein.S \
lib/cpus/aarch64/cortex_matterhorn.S \ lib/cpus/aarch64/cortex_matterhorn.S \

2
plat/arm/board/rddaniel/platform.mk
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@ -12,7 +12,7 @@ RDDANIEL_BASE = plat/arm/board/rddaniel
PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/ PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
BL1_SOURCES += ${SGI_CPU_SOURCES} \ BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIEL_BASE}/rddaniel_err.c ${RDDANIEL_BASE}/rddaniel_err.c

2
plat/arm/board/rddanielxlr/platform.mk
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@ -13,7 +13,7 @@ RDDANIELXLR_BASE = plat/arm/board/rddanielxlr
PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/ PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
BL1_SOURCES += ${SGI_CPU_SOURCES} \ BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIELXLR_BASE}/rddanielxlr_err.c ${RDDANIELXLR_BASE}/rddanielxlr_err.c