Merge changes Iba51bff1,I3f563cff into integration
* changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well
This commit is contained in:
commit
4a6b33ec17
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@ -39,7 +39,7 @@ typedef enum {
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CB_MEM_TABLE = 16,
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CB_MEM_TABLE = 16,
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} coreboot_memory_t;
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} coreboot_memory_t;
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coreboot_memory_t coreboot_get_memory_type(uintptr_t address);
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coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size);
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void coreboot_table_setup(void *base);
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void coreboot_table_setup(void *base);
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#endif /* COREBOOT_H */
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#endif /* COREBOOT_H */
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@ -89,7 +89,7 @@ static void setup_cbmem_console(uintptr_t baseaddr)
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CONSOLE_FLAG_CRASH);
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CONSOLE_FLAG_CRASH);
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}
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}
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coreboot_memory_t coreboot_get_memory_type(uintptr_t address)
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coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size)
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{
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{
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int i;
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int i;
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@ -98,9 +98,11 @@ coreboot_memory_t coreboot_get_memory_type(uintptr_t address)
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if (range->type == CB_MEM_NONE)
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if (range->type == CB_MEM_NONE)
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break; /* end of table reached */
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break; /* end of table reached */
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if (address >= range->start &&
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if ((start >= range->start) &&
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address - range->start < range->size)
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(start - range->start < range->size) &&
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(size <= range->size - (start - range->start))) {
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return range->type;
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return range->type;
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}
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}
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}
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return CB_MEM_NONE;
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return CB_MEM_NONE;
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@ -12,6 +12,14 @@
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* development platforms
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* development platforms
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*/
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*/
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/*
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* Defines used to retrieve QTI SOC Version
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*/
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#define JEDEC_QTI_BKID U(0x0)
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#define JEDEC_QTI_MFID U(0x70)
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#define QTI_SOC_CONTINUATION_SHIFT U(24)
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#define QTI_SOC_IDENTIFICATION_SHIFT U(16)
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/* Size of cacheable stacks */
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_STACK_SIZE 0x1000
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@ -11,7 +11,10 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <services/arm_arch_svc.h>
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#include <platform_def.h>
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#include <platform_def.h>
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#include <qti_plat.h>
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#include <qti_plat.h>
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@ -146,3 +149,46 @@ int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
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qti_align_mem_region(base_va, size, &base_va, &size);
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qti_align_mem_region(base_va, size, &base_va, &size);
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return mmap_remove_dynamic_region(base_va, size);
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return mmap_remove_dynamic_region(base_va, size);
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}
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}
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/*
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* This function returns soc version which mainly consist of below fields
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*
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* soc_version[30:24] = JEP-106 continuation code for the SiP
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* soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
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* soc_version[0:15] = Implementation defined SoC ID
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*/
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int32_t plat_get_soc_version(void)
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{
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uint32_t soc_version = (QTI_SOC_VERSION & QTI_SOC_VERSION_MASK);
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uint32_t jep106az_code = (JEDEC_QTI_BKID << QTI_SOC_CONTINUATION_SHIFT)
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| (JEDEC_QTI_MFID << QTI_SOC_IDENTIFICATION_SHIFT);
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return (int32_t)(jep106az_code | (soc_version));
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}
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/*
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* This function returns soc revision in below format
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*
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* soc_revision[0:30] = SOC revision of specific SOC
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*/
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int32_t plat_get_soc_revision(void)
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{
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return mmio_read_32(QTI_SOC_REVISION_REG) & QTI_SOC_REVISION_MASK;
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}
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/*****************************************************************************
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* plat_smccc_feature_available() - This function checks whether SMCCC feature
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* is availabile for the platform or not.
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* @fid: SMCCC function id
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*
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* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
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* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
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*****************************************************************************/
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int32_t plat_smccc_feature_available(u_register_t fid)
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{
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switch (fid) {
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case SMCCC_ARCH_SOC_ID:
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return SMC_ARCH_CALL_SUCCESS;
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default:
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return SMC_ARCH_CALL_NOT_SUPPORTED;
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}
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}
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@ -27,7 +27,7 @@
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*/
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*/
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#define QTI_SIP_SVC_CALL_COUNT_ID U(0x0200ff00)
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#define QTI_SIP_SVC_CALL_COUNT_ID U(0x0200ff00)
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#define QTI_SIP_SVC_UID_ID U(0x0200ff01)
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#define QTI_SIP_SVC_UID_ID U(0x0200ff01)
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/* 0x8200ff02 is reserved */
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/* 0x8200ff02 is reserved*/
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#define QTI_SIP_SVC_VERSION_ID U(0x0200ff03)
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#define QTI_SIP_SVC_VERSION_ID U(0x0200ff03)
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/*
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/*
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@ -97,37 +97,52 @@ bool qti_mem_assign_validate_param(memprot_info_t *mem_info,
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|| (src_vm_list_cnt >= QTI_VM_LAST) || (dst_vm_list_cnt == 0)
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|| (src_vm_list_cnt >= QTI_VM_LAST) || (dst_vm_list_cnt == 0)
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|| (dst_vm_list_cnt >= QTI_VM_LAST) || (u_num_mappings == 0)
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|| (dst_vm_list_cnt >= QTI_VM_LAST) || (u_num_mappings == 0)
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|| u_num_mappings > QTI_VM_MAX_LIST_SIZE) {
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|| u_num_mappings > QTI_VM_MAX_LIST_SIZE) {
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ERROR("vm count is 0 or more then QTI_VM_LAST or empty list\n");
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ERROR("source_vm_list %p dest_vm_list %p mem_info %p src_vm_list_cnt %u dst_vm_list_cnt %u u_num_mappings %u\n",
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source_vm_list, dest_vm_list, mem_info,
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(unsigned int)src_vm_list_cnt,
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(unsigned int)dst_vm_list_cnt,
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(unsigned int)u_num_mappings);
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return false;
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return false;
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}
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}
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for (i = 0; i < u_num_mappings; i++) {
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for (i = 0; i < u_num_mappings; i++) {
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if ((mem_info[i].mem_addr & (SIZE4K - 1))
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if ((mem_info[i].mem_addr & (SIZE4K - 1))
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|| (mem_info[i].mem_size == 0)
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|| (mem_info[i].mem_size & (SIZE4K - 1))) {
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|| (mem_info[i].mem_size & (SIZE4K - 1))) {
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ERROR("mem_info passed buffer 0x%x or size 0x%x is not 4k aligned\n",
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(unsigned int)mem_info[i].mem_addr,
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(unsigned int)mem_info[i].mem_size);
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return false;
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return false;
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}
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}
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if ((mem_info[i].mem_addr + mem_info[i].mem_size) <
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if ((mem_info[i].mem_addr + mem_info[i].mem_size) <
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mem_info[i].mem_addr) {
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mem_info[i].mem_addr) {
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ERROR("overflow in mem_addr 0x%x add mem_size 0x%x\n",
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(unsigned int)mem_info[i].mem_addr,
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(unsigned int)mem_info[i].mem_size);
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return false;
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return false;
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}
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}
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if (coreboot_get_memory_type(mem_info[i].mem_addr) !=
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coreboot_memory_t mem_type = coreboot_get_memory_type(
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CB_MEM_RAM) {
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mem_info[i].mem_addr,
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mem_info[i].mem_size);
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if (mem_type != CB_MEM_RAM && mem_type != CB_MEM_RESERVED) {
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ERROR("memory region not in CB MEM RAM or RESERVED area: region start 0x%x size 0x%x\n",
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(unsigned int)mem_info[i].mem_addr,
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(unsigned int)mem_info[i].mem_size);
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return false;
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return false;
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}
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}
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if (coreboot_get_memory_type
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(mem_info[i].mem_addr + mem_info[i].mem_size) !=
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CB_MEM_RAM) {
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return false;
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}
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}
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}
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for (i = 0; i < src_vm_list_cnt; i++) {
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for (i = 0; i < src_vm_list_cnt; i++) {
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if (source_vm_list[i] >= QTI_VM_LAST) {
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if (source_vm_list[i] >= QTI_VM_LAST) {
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ERROR("source_vm_list[%d] 0x%x is more then QTI_VM_LAST\n",
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i, (unsigned int)source_vm_list[i]);
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return false;
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return false;
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}
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}
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}
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}
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for (i = 0; i < dst_vm_list_cnt; i++) {
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for (i = 0; i < dst_vm_list_cnt; i++) {
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if (dest_vm_list[i].dst_vm >= QTI_VM_LAST) {
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if (dest_vm_list[i].dst_vm >= QTI_VM_LAST) {
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ERROR("dest_vm_list[%d] 0x%x is more then QTI_VM_LAST\n",
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i, (unsigned int)dest_vm_list[i].dst_vm);
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return false;
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return false;
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}
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}
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}
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}
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@ -150,6 +165,7 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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}
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}
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/* Validate input arg count & retrieve arg3-6 from NS Buffer. */
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/* Validate input arg count & retrieve arg3-6 from NS Buffer. */
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if ((x1 != QTI_SIP_SVC_MEM_ASSIGN_PARAM_ID) || (x5 == 0x0)) {
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if ((x1 != QTI_SIP_SVC_MEM_ASSIGN_PARAM_ID) || (x5 == 0x0)) {
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ERROR("invalid mem_assign param id or no mapping info\n");
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goto unmap_return;
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goto unmap_return;
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}
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}
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@ -160,6 +176,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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SMC_32) ? (sizeof(uint32_t) * 4) : (sizeof(uint64_t) * 4);
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SMC_32) ? (sizeof(uint32_t) * 4) : (sizeof(uint64_t) * 4);
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if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size,
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if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size,
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(MT_NS | MT_RO_DATA)) != 0) {
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(MT_NS | MT_RO_DATA)) != 0) {
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ERROR("map failed for params NS Buffer %x %x\n",
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(unsigned int)dyn_map_start, (unsigned int)dyn_map_size);
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goto unmap_return;
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goto unmap_return;
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}
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}
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/* Retrieve indirect args. */
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/* Retrieve indirect args. */
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@ -174,6 +192,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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}
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}
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/* Un-Map NS Buffer. */
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/* Un-Map NS Buffer. */
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if (qti_mmap_remove_dynamic_region(dyn_map_start, dyn_map_size) != 0) {
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if (qti_mmap_remove_dynamic_region(dyn_map_start, dyn_map_size) != 0) {
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ERROR("unmap failed for params NS Buffer %x %x\n",
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(unsigned int)dyn_map_start, (unsigned int)dyn_map_size);
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goto unmap_return;
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goto unmap_return;
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}
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}
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@ -191,6 +211,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size,
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if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size,
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(MT_NS | MT_RO_DATA)) != 0) {
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(MT_NS | MT_RO_DATA)) != 0) {
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ERROR("map failed for params NS Buffer2 %x %x\n",
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(unsigned int)dyn_map_start, (unsigned int)dyn_map_size);
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goto unmap_return;
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goto unmap_return;
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}
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}
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memprot_info_t *mem_info_p = (memprot_info_t *) x2;
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memprot_info_t *mem_info_p = (memprot_info_t *) x2;
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@ -205,6 +227,7 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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source_vm_list_p, src_vm_list_cnt,
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source_vm_list_p, src_vm_list_cnt,
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dest_vm_list_p,
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dest_vm_list_p,
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dst_vm_list_cnt) != true) {
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dst_vm_list_cnt) != true) {
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ERROR("Param validation failed\n");
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goto unmap_return;
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goto unmap_return;
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}
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}
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@ -219,8 +242,7 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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for (int i = 0; i < dst_vm_list_cnt; i++) {
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for (int i = 0; i < dst_vm_list_cnt; i++) {
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dest_vm_list[i].dst_vm = dest_vm_list_p[i].dst_vm;
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dest_vm_list[i].dst_vm = dest_vm_list_p[i].dst_vm;
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dest_vm_list[i].dst_vm_perm =
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dest_vm_list[i].dst_vm_perm = dest_vm_list_p[i].dst_vm_perm;
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dest_vm_list_p[i].dst_vm_perm;
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dest_vm_list[i].ctx = dest_vm_list_p[i].ctx;
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dest_vm_list[i].ctx = dest_vm_list_p[i].ctx;
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dest_vm_list[i].ctx_size = dest_vm_list_p[i].ctx_size;
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dest_vm_list[i].ctx_size = dest_vm_list_p[i].ctx_size;
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}
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}
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@ -233,6 +255,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc,
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/* Un-Map NS Buffers. */
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/* Un-Map NS Buffers. */
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if (qti_mmap_remove_dynamic_region(dyn_map_start,
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if (qti_mmap_remove_dynamic_region(dyn_map_start,
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dyn_map_size) != 0) {
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dyn_map_size) != 0) {
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ERROR("unmap failed for params NS Buffer %x %x\n",
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(unsigned int)dyn_map_start, (unsigned int)dyn_map_size);
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goto unmap_return;
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goto unmap_return;
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}
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}
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/* Invoke API lib api. */
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/* Invoke API lib api. */
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@ -13,12 +13,6 @@
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#define BL31_BASE 0x80b00000
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#define BL31_BASE 0x80b00000
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#define BL31_SIZE 0x00100000
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#define BL31_SIZE 0x00100000
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/*----------------------------------------------------------------------------*/
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/* AOP CMD DB address space for mapping */
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/*----------------------------------------------------------------------------*/
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#define QTI_AOP_CMD_DB_BASE 0x80820000
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#define QTI_AOP_CMD_DB_SIZE 0x00020000
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/* Chipset specific secure interrupt number/ID defs. */
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/* Chipset specific secure interrupt number/ID defs. */
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#define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204)
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#define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204)
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#define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21)
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#define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21)
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@ -178,5 +178,17 @@
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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#define QTI_PS_HOLD_REG 0x0C264000
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#define QTI_PS_HOLD_REG 0x0C264000
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* AOP CMD DB address space for mapping */
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/*----------------------------------------------------------------------------*/
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#define QTI_AOP_CMD_DB_BASE 0x80820000
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#define QTI_AOP_CMD_DB_SIZE 0x00020000
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/*----------------------------------------------------------------------------*/
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/* SOC hw version register */
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/*----------------------------------------------------------------------------*/
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#define QTI_SOC_VERSION U(0x7180)
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#define QTI_SOC_VERSION_MASK U(0xFFFF)
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#define QTI_SOC_REVISION_REG 0x1FC8000
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#define QTI_SOC_REVISION_MASK U(0xFFFF)
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/*----------------------------------------------------------------------------*/
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#endif /* PLATFORM_DEF_H */
|
#endif /* PLATFORM_DEF_H */
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||||||
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