Merge "fix(bl1): invalidate SP in data cache during secure SMC" into integration
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4cafcc30ed
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -118,6 +118,14 @@ func smc_handler
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mov r0, #DISABLE_DCACHE
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mov r0, #DISABLE_DCACHE
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bl enable_mmu_svc_mon
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bl enable_mmu_svc_mon
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/*
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* Invalidate `smc_ctx_t` in data cache to prevent dirty data being
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* used.
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*/
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mov r0, r6
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mov r1, #SMC_CTX_SIZE
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bl inv_dcache_range
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/* Enable the data cache. */
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/* Enable the data cache. */
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ldcopr r9, SCTLR
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ldcopr r9, SCTLR
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orr r9, r9, #SCTLR_C_BIT
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orr r9, r9, #SCTLR_C_BIT
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