GICv3: Allow either G1S or G0 interrupts to be configured
Currently the GICv3 driver mandates that platform populate both G1S and G0 interrupts. However, it is possible that a given platform is not interested in both the groups and just needs to specify either one of them. This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()` functions to allow either G1S or G0 interrupts to be configured. Fixes ARM-software/tf-issues#400 Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b
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@ -120,10 +120,12 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
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******************************************************************************/
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******************************************************************************/
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void gicv3_distif_init(void)
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void gicv3_distif_init(void)
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{
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{
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unsigned int bitmap = 0;
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assert(driver_data);
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assert(driver_data);
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assert(driver_data->gicd_base);
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assert(driver_data->gicd_base);
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assert(driver_data->g1s_interrupt_array);
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assert(driver_data->g1s_interrupt_array ||
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assert(driver_data->g0_interrupt_array);
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driver_data->g0_interrupt_array);
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assert(IS_IN_EL3());
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assert(IS_IN_EL3());
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@ -146,21 +148,25 @@ void gicv3_distif_init(void)
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gicv3_spis_configure_defaults(driver_data->gicd_base);
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gicv3_spis_configure_defaults(driver_data->gicd_base);
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/* Configure the G1S SPIs */
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/* Configure the G1S SPIs */
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gicv3_secure_spis_configure(driver_data->gicd_base,
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if (driver_data->g1s_interrupt_array) {
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gicv3_secure_spis_configure(driver_data->gicd_base,
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driver_data->g1s_interrupt_num,
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driver_data->g1s_interrupt_num,
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driver_data->g1s_interrupt_array,
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driver_data->g1s_interrupt_array,
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INTR_GROUP1S);
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INTR_GROUP1S);
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bitmap |= CTLR_ENABLE_G1S_BIT;
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}
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/* Configure the G0 SPIs */
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/* Configure the G0 SPIs */
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gicv3_secure_spis_configure(driver_data->gicd_base,
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if (driver_data->g0_interrupt_array) {
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gicv3_secure_spis_configure(driver_data->gicd_base,
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driver_data->g0_interrupt_num,
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driver_data->g0_interrupt_num,
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driver_data->g0_interrupt_array,
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driver_data->g0_interrupt_array,
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INTR_GROUP0);
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INTR_GROUP0);
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bitmap |= CTLR_ENABLE_G0_BIT;
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}
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/* Enable the secure SPIs now that they have been configured */
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/* Enable the secure SPIs now that they have been configured */
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gicd_set_ctlr(driver_data->gicd_base,
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gicd_set_ctlr(driver_data->gicd_base, bitmap, RWP_TRUE);
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CTLR_ENABLE_G1S_BIT | CTLR_ENABLE_G0_BIT,
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RWP_TRUE);
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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@ -177,8 +183,8 @@ void gicv3_rdistif_init(unsigned int proc_num)
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assert(driver_data->rdistif_base_addrs);
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assert(driver_data->rdistif_base_addrs);
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assert(driver_data->gicd_base);
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assert(driver_data->gicd_base);
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assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT);
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assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT);
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assert(driver_data->g1s_interrupt_array);
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assert(driver_data->g1s_interrupt_array ||
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assert(driver_data->g0_interrupt_array);
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driver_data->g0_interrupt_array);
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assert(IS_IN_EL3());
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assert(IS_IN_EL3());
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@ -188,16 +194,20 @@ void gicv3_rdistif_init(unsigned int proc_num)
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gicv3_ppi_sgi_configure_defaults(gicr_base);
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gicv3_ppi_sgi_configure_defaults(gicr_base);
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/* Configure the G1S SGIs/PPIs */
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/* Configure the G1S SGIs/PPIs */
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gicv3_secure_ppi_sgi_configure(gicr_base,
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if (driver_data->g1s_interrupt_array) {
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driver_data->g1s_interrupt_num,
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gicv3_secure_ppi_sgi_configure(gicr_base,
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driver_data->g1s_interrupt_array,
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driver_data->g1s_interrupt_num,
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INTR_GROUP1S);
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driver_data->g1s_interrupt_array,
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INTR_GROUP1S);
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}
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/* Configure the G0 SGIs/PPIs */
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/* Configure the G0 SGIs/PPIs */
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gicv3_secure_ppi_sgi_configure(gicr_base,
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if (driver_data->g0_interrupt_array) {
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driver_data->g0_interrupt_num,
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gicv3_secure_ppi_sgi_configure(gicr_base,
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driver_data->g0_interrupt_array,
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driver_data->g0_interrupt_num,
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INTR_GROUP0);
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driver_data->g0_interrupt_array,
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INTR_GROUP0);
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}
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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