Ensure the correct execution of TLBI instructions
After executing a TLBI a DSB is needed to ensure completion of the TLBI. rk3328: The MMU is allowed to load TLB entries for as long as it is enabled. Because of this, the correct place to execute a TLBI is right after disabling the MMU. Change-Id: I8280f248d10b49a8c354a4ccbdc8f8345ac4c170 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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@ -187,6 +187,7 @@ func smc_handler64
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bl disable_mmu_icache_el3
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bl disable_mmu_icache_el3
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tlbi alle3
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tlbi alle3
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dsb ish /* ERET implies ISB, so it is not needed here */
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#if SPIN_ON_BL1_EXIT
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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bl print_debug_loop_message
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@ -591,8 +591,10 @@ err_loop:
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__sramfunc void sram_suspend(void)
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__sramfunc void sram_suspend(void)
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{
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{
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/* disable mmu and icache */
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/* disable mmu and icache */
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tlbialle3();
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disable_mmu_icache_el3();
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disable_mmu_icache_el3();
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tlbialle3();
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dsbsy();
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isb();
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
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((uintptr_t)&pmu_cpuson_entrypoint >> CPU_BOOT_ADDR_ALIGN) |
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((uintptr_t)&pmu_cpuson_entrypoint >> CPU_BOOT_ADDR_ALIGN) |
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@ -54,6 +54,7 @@ void secure_partition_setup(void)
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/* Invalidate TLBs at EL1. */
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/* Invalidate TLBs at EL1. */
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tlbivmalle1();
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tlbivmalle1();
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dsbish();
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/*
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/*
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* General-Purpose registers
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* General-Purpose registers
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