Merge "mediatek: mt8192: add GIC600 support" into integration
This commit is contained in:
commit
7ad39818b1
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@ -15,6 +15,7 @@
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#include <lib/coreboot.h>
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#include <lib/coreboot.h>
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/* Platform Includes */
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/* Platform Includes */
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#include <mt_gic_v3.h>
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#include <plat_params.h>
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#include <plat_params.h>
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#include <plat_private.h>
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#include <plat_private.h>
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@ -79,6 +80,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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******************************************************************************/
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******************************************************************************/
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void bl31_platform_setup(void)
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void bl31_platform_setup(void)
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{
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{
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/* Initialize the GIC driver, CPU and distributor interfaces */
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mt_gic_driver_init();
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mt_gic_init();
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_GIC_V3_H
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#define MT_GIC_V3_H
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#include <drivers/arm/gicv3.h>
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#include <lib/mmio.h>
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void mt_gic_driver_init(void);
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void mt_gic_init(void);
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void mt_gic_set_pending(uint32_t irq);
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void mt_gic_distif_save(void);
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void mt_gic_distif_restore(void);
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void mt_gic_rdistif_init(void);
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void mt_gic_rdistif_save(void);
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void mt_gic_rdistif_restore(void);
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void mt_gic_rdistif_restore_all(void);
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void gic_sgi_save_all(void);
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void gic_sgi_restore_all(void);
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#endif /* MT_GIC_V3_H */
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@ -24,8 +24,8 @@ cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ---------------------------------------------
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/* ---------------------------------------------
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* The below macro prints out relevant GIC and
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* The below macro prints out relevant GIC
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* CCI registers whenever an unhandled exception
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* registers whenever an unhandled exception
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* is taken in BL31.
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* is taken in BL31.
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* Clobbers: x0 - x10, x26, x27, sp
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* Clobbers: x0 - x10, x26, x27, sp
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* ---------------------------------------------
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* ---------------------------------------------
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@ -38,6 +38,14 @@
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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#define SYS_COUNTER_FREQ_IN_MHZ 13
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#define SYS_COUNTER_FREQ_IN_MHZ 13
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE MT_GIC_BASE
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#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
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/*******************************************************************************
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/*******************************************************************************
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* Platform binary types for linking
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* Platform binary types for linking
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******************************************************************************/
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******************************************************************************/
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@ -0,0 +1,177 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "../drivers/arm/gic/v3/gicv3_private.h"
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#include <bl31/interrupt_mgmt.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <mt_gic_v3.h>
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#include <mtk_plat_common.h>
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#include <plat/common/platform.h>
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#include <plat_private.h>
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#include <platform_def.h>
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#define SGI_MASK 0xffff
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
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/* we save and restore the GICv3 context on system suspend */
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gicv3_dist_ctx_t dist_ctx;
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static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
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{
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return plat_core_pos_by_mpidr(mpidr);
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}
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gicv3_driver_data_t mt_gicv3_data = {
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.gicd_base = MT_GIC_BASE,
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.gicr_base = MT_GIC_RDIST_BASE,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = mt_mpidr_to_core_pos,
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};
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struct gic_chip_data {
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/* All cores share the same configuration */
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unsigned int saved_group;
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unsigned int saved_enable;
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unsigned int saved_conf0;
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unsigned int saved_conf1;
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unsigned int saved_grpmod;
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/* Per-core sgi */
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unsigned int saved_sgi[PLATFORM_CORE_COUNT];
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};
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static struct gic_chip_data gic_data;
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void mt_gic_driver_init(void)
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{
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gicv3_driver_init(&mt_gicv3_data);
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}
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void mt_gic_set_pending(uint32_t irq)
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{
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gicv3_set_interrupt_pending(irq, plat_my_core_pos());
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}
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void mt_gic_distif_save(void)
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{
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gicv3_distif_save(&dist_ctx);
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}
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void mt_gic_distif_restore(void)
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{
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gicv3_distif_init_restore(&dist_ctx);
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}
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void mt_gic_rdistif_init(void)
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{
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unsigned int proc_num;
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unsigned int index;
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uintptr_t gicr_base;
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proc_num = plat_my_core_pos();
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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/* set all SGI/PPI as non-secure GROUP1 by default */
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mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
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mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
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/* setup the default PPI/SGI priorities */
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for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
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gicr_write_ipriorityr(gicr_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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void mt_gic_rdistif_save(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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proc_num = plat_my_core_pos();
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
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gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
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gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
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gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
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gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
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rdist_has_saved[proc_num] = 1;
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}
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void mt_gic_rdistif_restore(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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proc_num = plat_my_core_pos();
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if (rdist_has_saved[proc_num] == 1) {
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
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mmio_write_32(gicr_base + GICR_ISENABLER0,
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gic_data.saved_enable);
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mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
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mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
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mmio_write_32(gicr_base + GICR_IGRPMODR0,
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gic_data.saved_grpmod);
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}
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}
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void mt_gic_rdistif_restore_all(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
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mmio_write_32(gicr_base + GICR_ISENABLER0,
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gic_data.saved_enable);
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mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
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mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
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mmio_write_32(gicr_base + GICR_IGRPMODR0,
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gic_data.saved_grpmod);
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}
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}
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void gic_sgi_save_all(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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gic_data.saved_sgi[proc_num] =
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mmio_read_32(gicr_base + GICR_ISPENDR0) & SGI_MASK;
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}
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}
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void gic_sgi_restore_all(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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mmio_write_32(gicr_base + GICR_ICPENDR0, SGI_MASK);
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mmio_write_32(gicr_base + GICR_ISPENDR0,
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gic_data.saved_sgi[proc_num] & SGI_MASK);
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}
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}
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void mt_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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@ -10,6 +10,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
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PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT_SOC}/include/
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-I${MTK_PLAT_SOC}/include/
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GICV3_SUPPORT_GIC600 := 1
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include drivers/arm/gic/v3/gicv3.mk
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include drivers/arm/gic/v3/gicv3.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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@ -30,7 +31,8 @@ BL31_SOURCES += common/desc_image_load.c \
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${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
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${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
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${MTK_PLAT_SOC}/bl31_plat_setup.c \
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${MTK_PLAT_SOC}/bl31_plat_setup.c \
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${MTK_PLAT_SOC}/plat_pm.c \
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${MTK_PLAT_SOC}/plat_pm.c \
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${MTK_PLAT_SOC}/plat_topology.c
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${MTK_PLAT_SOC}/plat_topology.c \
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${MTK_PLAT_SOC}/plat_mt_gic.c
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# Configs for A76 and A55
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# Configs for A76 and A55
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