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Merge pull request #1674 from jforissier/hisi-multi-console 

hikey, hikey960, poplar: use new console APIs
This commit is contained in:
Antonio Niño Díaz 2018-11-12 11:40:11 +01:00 committed by GitHub
parent e07666de14 5c58c8b1ee
commit 91ece4e2c8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 49 additions and 28 deletions
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6
plat/hisilicon/hikey/aarch64/hikey_helpers.S
View File

@ -46,7 +46,7 @@ func plat_crash_console_init
mov_imm x0, CRASH_CONSOLE_BASE
mov_imm x1, PL011_UART_CLK_IN_HZ
mov_imm x2, PL011_BAUDRATE
b console_core_init
b console_pl011_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
@ -58,7 +58,7 @@ endfunc plat_crash_console_init
*/
func plat_crash_console_putc
mov_imm x1, CRASH_CONSOLE_BASE
b console_core_putc
b console_pl011_core_putc
endfunc plat_crash_console_putc
/* ---------------------------------------------
@ -71,7 +71,7 @@ endfunc plat_crash_console_putc
*/
func plat_crash_console_flush
mov_imm x0, CRASH_CONSOLE_BASE
b console_core_flush
b console_pl011_core_flush
endfunc plat_crash_console_flush
/* ---------------------------------------------

6
plat/hisilicon/hikey/hikey_bl1_setup.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <dw_mmc.h>
#include <errno.h>
@ -16,6 +15,7 @@
#include <hikey_layout.h>
#include <mmc.h>
#include <mmio.h>
#include <pl011.h>
#include <platform.h>
#include <string.h>
#include <tbbr/tbbr_img_desc.h>
@ -25,6 +25,7 @@
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
static console_pl011_t console;
enum {
BOOT_NORMAL = 0,
@ -43,7 +44,8 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
void bl1_early_platform_setup(void)
{
/* Initialize the console to provide early debug support */
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL1_RW_BASE;

6
plat/hisilicon/hikey/hikey_bl2_setup.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <delay_timer.h>
#include <desc_image_load.h>
@ -21,6 +20,7 @@
#ifdef SPD_opteed
#include <optee_utils.h>
#endif
#include <pl011.h>
#include <platform.h>
#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
#include <string.h>
@ -49,6 +49,7 @@
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
enum {
BOOT_MODE_RECOVERY = 0,
@ -279,7 +280,8 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
u_register_t arg3, u_register_t arg4)
{
/* Initialize the console to provide early debug support */
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/*
* Allow BL2 to see the whole Trusted RAM.
*/

6
plat/hisilicon/hikey/hikey_bl31_setup.c
View File

@ -8,7 +8,6 @@
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
#include <console.h>
#include <debug.h>
#include <errno.h>
#include <gicv2.h>
@ -18,6 +17,7 @@
#include <hisi_pwrc.h>
#include <interrupt_props.h>
#include <mmio.h>
#include <pl011.h>
#include <platform_def.h>
#include "hikey_private.h"
@ -43,6 +43,7 @@
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static console_pl011_t console;
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
@ -92,7 +93,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
from_bl2 = (void *) arg0;
/* Initialize the console to provide early debug support */
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Initialize CCI driver */
cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));

1
plat/hisilicon/hikey/platform.mk
View File

@ -20,6 +20,7 @@ endif
CONSOLE_BASE := PL011_UART3_BASE
CRASH_CONSOLE_BASE := PL011_UART3_BASE
MULTI_CONSOLE_API := 1
PLAT_PARTITION_MAX_ENTRIES := 12
PLAT_PL061_MAX_GPIOS := 160
COLD_BOOT_SINGLE_CPU := 1

6
plat/hisilicon/hikey960/aarch64/hikey960_helpers.S
View File

@ -50,7 +50,7 @@ func plat_crash_console_init
mov_imm x0, CRASH_CONSOLE_BASE
mov_imm x1, PL011_UART_CLK_IN_HZ
mov_imm x2, PL011_BAUDRATE
b console_core_init
b console_pl011_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
@ -62,7 +62,7 @@ endfunc plat_crash_console_init
*/
func plat_crash_console_putc
mov_imm x1, CRASH_CONSOLE_BASE
b console_core_putc
b console_pl011_core_putc
endfunc plat_crash_console_putc
/* ---------------------------------------------
@ -75,7 +75,7 @@ endfunc plat_crash_console_putc
*/
func plat_crash_console_flush
mov_imm x0, CRASH_CONSOLE_BASE
b console_core_flush
b console_pl011_core_flush
endfunc plat_crash_console_flush
/* ---------------------------------------------

6
plat/hisilicon/hikey960/hikey960_bl1_setup.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <delay_timer.h>
#include <dw_ufs.h>
@ -17,6 +16,7 @@
#include <hi3660.h>
#include <interrupt_props.h>
#include <mmio.h>
#include <pl011.h>
#include <platform.h>
#include <platform_def.h>
#include <string.h>
@ -40,6 +40,7 @@ enum {
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
static console_pl011_t console;
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
@ -78,7 +79,8 @@ void bl1_early_platform_setup(void)
else
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL1_RW_BASE;

6
plat/hisilicon/hikey960/hikey960_bl2_setup.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <delay_timer.h>
#include <desc_image_load.h>
@ -19,6 +18,7 @@
#ifdef SPD_opteed
#include <optee_utils.h>
#endif
#include <pl011.h>
#include <platform_def.h>
#include <string.h>
#include <ufs.h>
@ -48,6 +48,7 @@
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
extern int load_lpm3(void);
enum {
@ -296,7 +297,8 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
else
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/*
* Allow BL2 to see the whole Trusted RAM.
*/

5
plat/hisilicon/hikey960/hikey960_bl31_setup.c
View File

@ -17,6 +17,7 @@
#include <hisi_ipc.h>
#include <interrupt_mgmt.h>
#include <interrupt_props.h>
#include <pl011.h>
#include <platform.h>
#include <platform_def.h>
@ -44,6 +45,7 @@
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static console_pl011_t console;
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
@ -96,7 +98,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Initialize CCI driver */
cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));

7
plat/hisilicon/hikey960/hikey960_pm.c
View File

@ -7,13 +7,13 @@
#include <arch_helpers.h>
#include <assert.h>
#include <cci.h>
#include <console.h>
#include <debug.h>
#include <delay_timer.h>
#include <gicv2.h>
#include <hi3660.h>
#include <hi3660_crg.h>
#include <mmio.h>
#include <pl011.h>
#include <psci.h>
#include "drivers/pwrc/hisi_pwrc.h"
@ -31,6 +31,7 @@
#define AXI_CONF_BASE 0x820
static unsigned int uart_base;
static console_pl011_t console;
static uintptr_t hikey960_sec_entrypoint;
static void hikey960_pwr_domain_standby(plat_local_state_t cpu_state)
@ -268,8 +269,8 @@ hikey960_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
if (hisi_test_ap_suspend_flag(cluster)) {
hikey960_sr_dma_reinit();
gicv2_cpuif_enable();
console_init(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE);
console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
}
hikey960_pwr_domain_on_finish(target_state);

1
plat/hisilicon/hikey960/platform.mk
View File

@ -17,6 +17,7 @@ else
$(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
endif
MULTI_CONSOLE_API := 1
CRASH_CONSOLE_BASE := PL011_UART6_BASE
COLD_BOOT_SINGLE_CPU := 1
PLAT_PL061_MAX_GPIOS := 176

6
plat/hisilicon/poplar/bl1_plat_setup.c
View File

@ -7,13 +7,13 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <dw_mmc.h>
#include <errno.h>
#include <generic_delay_timer.h>
#include <mmc.h>
#include <mmio.h>
#include <pl011.h>
#include <pl061_gpio.h>
#include <platform.h>
#include <platform_def.h>
@ -26,6 +26,7 @@
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
static meminfo_t bl2_tzram_layout;
static console_pl011_t console;
/*
* Cannot use default weak implementation in bl1_main.c because BL1 RW data is
@ -62,7 +63,8 @@ int bl1_plat_handle_post_image_load(unsigned int image_id)
void bl1_early_platform_setup(void)
{
/* Initialize the console to provide early debug support */
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL1_RW_BASE;

6
plat/hisilicon/poplar/bl2_plat_setup.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
#include <dw_mmc.h>
@ -17,6 +16,7 @@
#include <mmio.h>
#include <optee_utils.h>
#include <partition/partition.h>
#include <pl011.h>
#include <platform.h>
#include <string.h>
#include "hi3798cv200.h"
@ -31,6 +31,7 @@
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
static console_pl011_t console;
/*******************************************************************************
* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
@ -181,7 +182,8 @@ void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Enable arch timer */
generic_delay_timer_init();

6
plat/hisilicon/poplar/bl31_plat_setup.c
View File

@ -9,12 +9,12 @@
#include <assert.h>
#include <bl31.h>
#include <bl_common.h>
#include <console.h>
#include <cortex_a53.h>
#include <debug.h>
#include <errno.h>
#include <generic_delay_timer.h>
#include <mmio.h>
#include <pl011.h>
#include <platform.h>
#include <platform_def.h>
#include <stddef.h>
@ -34,6 +34,7 @@
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
static console_pl011_t console;
static void hisi_tzpc_sec_init(void)
{
@ -72,7 +73,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
from_bl2 = (void *) arg0;
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Init console for crash report */
plat_crash_console_init();

1
plat/hisilicon/poplar/plat_pm.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <context.h>
#include <context_mgmt.h>
#include <debug.h>

2
plat/hisilicon/poplar/platform.mk
View File

@ -46,7 +46,7 @@ ERRATA_A53_855873 := 1
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ENABLE_SVE_FOR_NS := 0
MULTI_CONSOLE_API := 1
WORKAROUND_CVE_2017_5715 := 0
PLAT_PL061_MAX_GPIOS := 104