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Merge changes Ic701675c,Ie55e25c8 into integration 

* changes:
  plat: imx8m: Correct the imr mask reg offset
  plat: imx8m: Keep A53 PLAT on in wait mode(ret)
This commit is contained in:
Manish Pandey 2020-08-19 11:27:58 +00:00 committed by TrustedFirmware Code Review
parent 9ce37110f5 fb9212be17
commit a3b500449b
7 changed files with 13 additions and 8 deletions
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10
plat/imx/imx8m/gpc_common.c
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@ -16,7 +16,7 @@
#include <imx8m_psci.h>
#include <plat_imx8.h>
static uint32_t gpc_imr_offset[] = { 0x30, 0x40, 0x1c0, 0x1d0, };
static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, };
#pragma weak imx_set_cpu_pwr_off
#pragma weak imx_set_cpu_pwr_on
@ -133,14 +133,12 @@ void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
val &= ~EN_L2_WFI_PDN;
/* L2 cache memory is on in WAIT mode */
if (is_local_state_off(power_state))
if (is_local_state_off(power_state)) {
val |= (L2PGE | EN_PLAT_PDN);
else
val |= EN_PLAT_PDN;
imx_a53_plat_slot_config(true);
}
mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
imx_a53_plat_slot_config(true);
} else {
/* clear the slot and ack for cluster power down */
imx_a53_plat_slot_config(false);

2
plat/imx/imx8m/imx8m_psci_common.c
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@ -192,7 +192,7 @@ void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
* drived by the 32K OSC, so delay 30us to make sure the counter
* is really running.
*/
if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) {
if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
imx_set_rbc_count();
udelay(30);
}

2
plat/imx/imx8m/imx8mm/include/gpc_reg.h
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@ -124,4 +124,6 @@
#define VPU_G2_PGC 0xf00
#define VPU_H1_PGC 0xf40
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */

2
plat/imx/imx8m/imx8mn/include/gpc_reg.h
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@ -106,4 +106,6 @@
#define GPUMIX_PGC 0xdc0
#define DISPMIX_PGC 0xe80
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */

2
plat/imx/imx8m/imx8mp/include/gpc_reg.h
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@ -146,4 +146,6 @@
#define MEDIAMIX_ISPDWP_PGC 0xf80
#define DDRMIX_PGC 0xfc0
#define IRQ_IMR_NUM U(5)
#endif /* GPC_REG_H */

2
plat/imx/imx8m/imx8mq/include/gpc_reg.h
View File

@ -84,4 +84,6 @@
#define MASTER1_MAPPING BIT(1)
#define MASTER2_MAPPING BIT(2)
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */

1
plat/imx/imx8m/include/gpc.h
View File

@ -25,7 +25,6 @@
#define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4)))
#define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2))
#define IRQ_IMR_NUM 4
#define IMR_MASK_ALL 0xffffffff
#define IMX_PD_DOMAIN(name, on) \