Merge "fix(errata): workarounds for cortex-x1 errata" into integration
This commit is contained in:
commit
c8c7c47bb3
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@ -322,6 +322,17 @@ For Cortex-A78 AE, the following errata build flags are defined :
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Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
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Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
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erratum is still open.
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erratum is still open.
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For Cortex-X1 CPU, the following errata build flags are defined:
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- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1
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CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
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- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1
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CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
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- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1
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CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
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For Neoverse N1, the following errata build flags are defined :
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For Neoverse N1, the following errata build flags are defined :
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- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
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- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
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@ -15,6 +15,11 @@
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******************************************************************************/
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******************************************************************************/
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#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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/*******************************************************************************
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* CPU Power Control register specific definitions
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* CPU Power Control register specific definitions
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******************************************************************************/
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******************************************************************************/
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@ -18,8 +18,116 @@
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#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#endif
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/* --------------------------------------------------
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* Errata Workaround for X1 Erratum 1821534.
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* This applies to revision r0p0 and r1p0 of X1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_x1_1821534_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1821534
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cbz x0, 1f
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mrs x1, CORTEX_X1_ACTLR2_EL1
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orr x1, x1, BIT(2)
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msr CORTEX_X1_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_x1_1821534_wa
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func check_errata_1821534
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1821534
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/* --------------------------------------------------
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* Errata Workaround for X1 Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of X1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_x1_1688305_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1688305
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cbz x0, 1f
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mrs x0, CORTEX_X1_ACTLR2_EL1
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orr x0, x0, BIT(1)
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msr CORTEX_X1_ACTLR2_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_x1_1688305_wa
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func check_errata_1688305
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* --------------------------------------------------
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* Errata Workaround for X1 Erratum 1827429.
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* This applies to revision r0p0 and r1p0 of X1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_x1_1827429_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1827429
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cbz x0, 1f
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mrs x0, CORTEX_X1_CPUECTLR_EL1
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orr x0, x0, BIT(53)
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msr CORTEX_X1_CPUECTLR_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_x1_1827429_wa
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func check_errata_1827429
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1827429
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-X1.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_x1_reset_func
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func cortex_x1_reset_func
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ret
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_X1_1821534
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mov x0, x18
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bl errata_x1_1821534_wa
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#endif
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#if ERRATA_X1_1688305
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mov x0, x18
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bl errata_x1_1688305_wa
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#endif
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#if ERRATA_X1_1827429
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mov x0, x18
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bl errata_x1_1827429_wa
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#endif
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isb
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ret x19
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endfunc cortex_x1_reset_func
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endfunc cortex_x1_reset_func
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/* ---------------------------------------------
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/* ---------------------------------------------
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@ -43,6 +151,20 @@ endfunc cortex_x1_core_pwr_dwn
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* Errata printing function for Cortex X1. Must follow AAPCS.
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* Errata printing function for Cortex X1. Must follow AAPCS.
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*/
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*/
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func cortex_x1_errata_report
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func cortex_x1_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_X1_1821534, cortex_x1, 1821534
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report_errata ERRATA_X1_1688305, cortex_x1, 1688305
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report_errata ERRATA_X1_1827429, cortex_x1, 1827429
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ldp x8, x30, [sp], #16
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ret
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ret
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endfunc cortex_x1_errata_report
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endfunc cortex_x1_errata_report
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#endif
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#endif
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@ -357,6 +357,18 @@ ERRATA_A78_AE_2376748 ?=0
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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ERRATA_A78_AE_2395408 ?=0
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ERRATA_A78_AE_2395408 ?=0
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# Flag to apply erratum 1821534 workaround during reset. This erratum applies
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# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
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ERRATA_X1_1821534 ?=0
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# Flag to apply erratum 1688305 workaround during reset. This erratum applies
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# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
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ERRATA_X1_1688305 ?=0
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# Flag to apply erratum 1827429 workaround during reset. This erratum applies
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# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
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ERRATA_X1_1827429 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=0
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ERRATA_N1_1043202 ?=0
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@ -878,6 +890,18 @@ $(eval $(call add_define,ERRATA_A78_AE_2376748))
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$(eval $(call assert_boolean,ERRATA_A78_AE_2395408))
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$(eval $(call assert_boolean,ERRATA_A78_AE_2395408))
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$(eval $(call add_define,ERRATA_A78_AE_2395408))
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$(eval $(call add_define,ERRATA_A78_AE_2395408))
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# Process ERRATA_X1_1821534 flag
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$(eval $(call assert_boolean,ERRATA_X1_1821534))
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$(eval $(call add_define,ERRATA_X1_1821534))
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# Process ERRATA_X1_1688305 flag
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$(eval $(call assert_boolean,ERRATA_X1_1688305))
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$(eval $(call add_define,ERRATA_X1_1688305))
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# Process ERRATA_X1_1827429 flag
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$(eval $(call assert_boolean,ERRATA_X1_1827429))
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$(eval $(call add_define,ERRATA_X1_1827429))
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# Process ERRATA_N1_1043202 flag
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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