Merge pull request #1474 from dp-arm/dp/cpus
Add initial CPU support for Cortex-Deimos and Cortex-Helios
This commit is contained in:
commit
df4c512d47
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __CORTEX_DEIMOS_H__
|
||||
#define __CORTEX_DEIMOS_H__
|
||||
|
||||
#define CORTEX_DEIMOS_MIDR U(0x410FD0D0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* __CORTEX_DEIMOS_H__ */
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __CORTEX_HELIOS_H__
|
||||
#define __CORTEX_HELIOS_H__
|
||||
|
||||
#define CORTEX_HELIOS_MIDR U(0x410FD060)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* __CORTEX_HELIOS_H__ */
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <bl_common.h>
|
||||
#include <cortex_deimos.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <plat_macros.S>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_deimos_core_pwr_dwn
|
||||
/* ---------------------------------------------
|
||||
* Enable CPU power down bit in power control register
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1
|
||||
orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
|
||||
msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_deimos_core_pwr_dwn
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides Cortex-Deimos specific
|
||||
* register information for crash reporting.
|
||||
* It needs to return with x6 pointing to
|
||||
* a list of register names in ascii and
|
||||
* x8 - x15 having values of registers to be
|
||||
* reported.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.section .rodata.cortex_deimos_regs, "aS"
|
||||
cortex_deimos_regs: /* The ascii list of register names to be reported */
|
||||
.asciz "cpuectlr_el1", ""
|
||||
|
||||
func cortex_deimos_cpu_reg_dump
|
||||
adr x6, cortex_deimos_regs
|
||||
mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1
|
||||
ret
|
||||
endfunc cortex_deimos_cpu_reg_dump
|
||||
|
||||
declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \
|
||||
CPU_NO_RESET_FUNC, \
|
||||
cortex_deimos_core_pwr_dwn
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <bl_common.h>
|
||||
#include <cortex_helios.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <debug.h>
|
||||
#include <plat_macros.S>
|
||||
|
||||
func cortex_helios_cpu_pwr_dwn
|
||||
mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1
|
||||
orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
|
||||
msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_helios_cpu_pwr_dwn
|
||||
|
||||
.section .rodata.cortex_helios_regs, "aS"
|
||||
cortex_helios_regs: /* The ascii list of register names to be reported */
|
||||
.asciz "cpuectlr_el1", ""
|
||||
|
||||
func cortex_helios_cpu_reg_dump
|
||||
adr x6, cortex_helios_regs
|
||||
mrs x8, CORTEX_HELIOS_ECTLR_EL1
|
||||
ret
|
||||
endfunc cortex_helios_cpu_reg_dump
|
||||
|
||||
declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \
|
||||
CPU_NO_RESET_FUNC, \
|
||||
cortex_helios_cpu_pwr_dwn
|
|
@ -116,7 +116,8 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
|
|||
lib/cpus/aarch64/cortex_a73.S \
|
||||
lib/cpus/aarch64/cortex_a75.S \
|
||||
lib/cpus/aarch64/cortex_a76.S \
|
||||
lib/cpus/aarch64/cortex_ares.S
|
||||
lib/cpus/aarch64/cortex_ares.S \
|
||||
lib/cpus/aarch64/cortex_deimos.S
|
||||
else
|
||||
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
|
||||
endif
|
||||
|
|
Loading…
Reference in New Issue