fix(include/aarch64): fix encodings for MPAMVPM* registers
This patch fixes the following encodings in the System register encoding space for the MPAM registers. The encodings now match with the Arm® Architecture Reference Manual Supplement for MPAM. * MPAMVPM0_EL2 * MPAMVPM1_EL2 * MPAMVPM2_EL2 * MPAMVPM3_EL2 * MPAMVPM4_EL2 * MPAMVPM5_EL2 * MPAMVPM6_EL2 * MPAMVPM7_EL2 * MPAMVPMV_EL2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ib339412de6a9c945a3307f3f347fe7b2efabdc18
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/*
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/*
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* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define HFGWTR_EL2 S3_4_C1_C1_5
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#define HFGWTR_EL2 S3_4_C1_C1_5
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#define ICH_HCR_EL2 S3_4_C12_C11_0
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#define ICH_HCR_EL2 S3_4_C12_C11_0
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#define ICH_VMCR_EL2 S3_4_C12_C11_7
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#define ICH_VMCR_EL2 S3_4_C12_C11_7
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#define MPAMVPM0_EL2 S3_4_C10_C5_0
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#define MPAMVPM0_EL2 S3_4_C10_C6_0
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#define MPAMVPM1_EL2 S3_4_C10_C5_1
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#define MPAMVPM1_EL2 S3_4_C10_C6_1
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#define MPAMVPM2_EL2 S3_4_C10_C5_2
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#define MPAMVPM2_EL2 S3_4_C10_C6_2
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#define MPAMVPM3_EL2 S3_4_C10_C5_3
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#define MPAMVPM3_EL2 S3_4_C10_C6_3
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#define MPAMVPM4_EL2 S3_4_C10_C5_4
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#define MPAMVPM4_EL2 S3_4_C10_C6_4
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#define MPAMVPM5_EL2 S3_4_C10_C5_5
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#define MPAMVPM5_EL2 S3_4_C10_C6_5
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#define MPAMVPM6_EL2 S3_4_C10_C5_6
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#define MPAMVPM6_EL2 S3_4_C10_C6_6
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#define MPAMVPM7_EL2 S3_4_C10_C5_7
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#define MPAMVPM7_EL2 S3_4_C10_C6_7
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#define MPAMVPMV_EL2 S3_4_C10_C4_1
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#define MPAMVPMV_EL2 S3_4_C10_C4_1
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#define TRFCR_EL2 S3_4_C1_C2_1
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#define TRFCR_EL2 S3_4_C1_C2_1
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#define PMSCR_EL2 S3_4_C9_C9_0
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#define PMSCR_EL2 S3_4_C9_C9_0
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