Merge "plat/intel: Fix SMPLSEL for MMC" into integration

2019-07-11 12:37:26 +00:00 · 2019-07-11 12:37:26 +00:00 · ec92cbcb6a
parent f15d7e8325 0943ea379f
commit ec92cbcb6a
2 changed files with 8 additions and 0 deletions
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@ -59,6 +59,11 @@
 #define S10_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
 #define S10_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628

+#define S10_SYSMGR_CORE(x)			(0xffd12000 + (x))
+#define SYSMGR_MMC				0x28
+#define SYSMGR_MMC_DRVSEL(x)			(((x) & 0x7) << 0)
+
+
 #define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))

 void enable_nonsecure_access(void);
--- a/plat/intel/soc/stratix10/soc/s10_system_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_system_manager.c
@ -86,5 +86,8 @@ void enable_nonsecure_access(void)

 	mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
 	mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
+
+	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
+
 }