corstone700: splitting the platform support into FVP and FPGA
This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
This commit is contained in:
parent
11af40b630
commit
ef93cfa3a2
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@ -1,22 +1,18 @@
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/*
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/*
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* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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/ {
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model = "corstone700";
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compatible = "arm,Corstone-700";
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compatible = "arm,Corstone-700";
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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chosen {
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chosen { };
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bootargs = "console=ttyAMA0 \
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loglevel=9";
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};
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cpus {
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cpus {
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#address-cells = <1>;
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#address-cells = <1>;
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@ -28,7 +24,6 @@
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reg = <0>;
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reg = <0>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&L2_0>;
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};
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};
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};
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};
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memory@80000000 {
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memory@80000000 {
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@ -99,7 +94,21 @@
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<1 14 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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<1 10 0xf08>;
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};
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refclk: refclk@1a220000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x1a220000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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frame@1a230000 {
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frame-number = <0>;
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interrupts = <0 2 0xf04>;
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reg = <0x1a230000 0x1000>;
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};
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};
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};
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mbox_es0mhu0: mhu@1b000000 {
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mbox_es0mhu0: mhu@1b000000 {
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compatible = "arm,mhuv2","arm,primecell";
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compatible = "arm,mhuv2","arm,primecell";
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@ -149,5 +158,4 @@
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<0x1A010314 0x4>;
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<0x1A010314 0x4>;
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reg-names = "rstreg", "streg";
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reg-names = "rstreg", "streg";
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};
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};
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};
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};
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include "corstone700.dtsi"
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/ {
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model = "corstone700-fpga";
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ethernet: eth@40100000 {
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compatible = "smsc,lan9115";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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};
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};
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&refclk {
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clock-frequency = <32000000>;
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};
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@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include "corstone700.dtsi"
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/ {
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model = "corstone700-fvp";
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/*
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* Intel StrataFlash J3 NOR flash: 2 x 16-bit interleaved components
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* Flash total size: 32 MB
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* Allocated flash space: 8 MB
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*/
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flash@8500000 {
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compatible = "cfi-flash";
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reg = <0x8500000 0x800000>;
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bank-width = <4>;
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device-width= <2>;
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};
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ethernet: eth@4010000 {
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compatible = "smsc,lan91c111";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 116 0xf04>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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};
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};
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&refclk {
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clock-frequency = <50000000>;
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};
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@ -18,6 +18,7 @@
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const mmap_region_t plat_arm_mmap[] = {
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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ARM_MAP_SHARED_RAM,
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ARM_MAP_NS_SHARED_RAM,
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ARM_MAP_NS_DRAM1,
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ARM_MAP_NS_DRAM1,
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CORSTONE700_MAP_DEVICE,
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CORSTONE700_MAP_DEVICE,
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{0}
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{0}
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@ -33,5 +34,6 @@ void __init plat_arm_pwrc_setup(void)
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unsigned int plat_get_syscnt_freq2(void)
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unsigned int plat_get_syscnt_freq2(void)
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{
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{
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return CORSTONE700_TIMER_BASE_FREQUENCY;
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/* Returning the Generic Timer Frequency */
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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}
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@ -67,6 +67,9 @@
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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ARM_SHARED_RAM_SIZE)
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#define ARM_NS_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE + UL(0x00100000)
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#define ARM_NS_SHARED_RAM_SIZE 0x00300000
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/*
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/*
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* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
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* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
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* the page reserved for fw_configs) to BL32
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* the page reserved for fw_configs) to BL32
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@ -111,7 +114,13 @@
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#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
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#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
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#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
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#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
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#define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
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#define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
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#define CORSTONE700_TIMER_BASE_FREQUENCY UL(24000000)
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#ifdef TARGET_PLATFORM_FVP
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#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */
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#else
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#define SYS_COUNTER_FREQ_IN_TICKS UL(32000000) /* 32MHz */
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#endif
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#define CORSTONE700_IRQ_TZ_WDOG 32
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#define CORSTONE700_IRQ_TZ_WDOG 32
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#define CORSTONE700_IRQ_SEC_SYS_TIMER 34
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#define CORSTONE700_IRQ_SEC_SYS_TIMER 34
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@ -140,7 +149,7 @@
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
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#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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ARM_SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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MT_MEMORY | MT_RW | MT_SECURE)
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#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
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ARM_NS_SHARED_RAM_BASE, \
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ARM_NS_SHARED_RAM_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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ARM_NS_DRAM1_BASE, \
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@ -4,6 +4,11 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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# Making sure the corstone700 platform type is specified
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ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
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$(error TARGET_PLATFORM must be fpga or fvp)
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endif
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CORSTONE700_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
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CORSTONE700_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
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BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \
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BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \
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lib/xlat_tables/aarch32/xlat_tables.c \
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lib/xlat_tables/aarch32/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/xlat_tables_common.c \
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${CORSTONE700_CPU_LIBS} \
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${CORSTONE700_CPU_LIBS} \
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plat/arm/board/corstone700/drivers/mhu/mhu.c
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plat/arm/board/corstone700/common/drivers/mhu/mhu.c
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PLAT_INCLUDES := -Iplat/arm/board/corstone700/include \
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PLAT_INCLUDES := -Iplat/arm/board/corstone700/common/include \
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-Iinclude/plat/arm/common \
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-Iinclude/plat/arm/common \
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-Iplat/arm/board/corstone700/drivers/mhu
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-Iplat/arm/board/corstone700/common/drivers/mhu
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NEED_BL32 := yes
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NEED_BL32 := yes
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override NEED_BL1 := no
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override NEED_BL1 := no
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override NEED_BL2 := no
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override NEED_BL2 := no
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override NEED_BL2U := no
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override NEED_BL2U := no
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override NEED_BL33 := yes
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#TFA for Corstone700 starts from BL32
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#TFA for Corstone700 starts from BL32
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override RESET_TO_SP_MIN := 1
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override RESET_TO_SP_MIN := 1
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#Device tree
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#Device tree
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CORSTONE700_HW_CONFIG_DTS := fdts/corstone700.dts
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CORSTONE700_HW_CONFIG_DTS := fdts/corstone700_${TARGET_PLATFORM}.dts
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CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
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CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/corstone700_${TARGET_PLATFORM}.dtb
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FDT_SOURCES += ${CORSTONE700_HW_CONFIG_DTS}
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FDT_SOURCES += ${CORSTONE700_HW_CONFIG_DTS}
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$(eval CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS)))
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$(eval CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS)))
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$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
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$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
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endif
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endif
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$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
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$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
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# Adding TARGET_PLATFORM as a GCC define (-D option)
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$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
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include plat/arm/board/common/board_common.mk
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include plat/arm/board/common/board_common.mk
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# SP_MIN source files specific to FVP platform
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# SP_MIN source files specific to FVP platform
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BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \
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BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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lib/utils/mem_region.c \
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plat/arm/board/corstone700/corstone700_helpers.S \
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plat/arm/board/corstone700/common/corstone700_helpers.S \
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plat/arm/board/corstone700/corstone700_topology.c \
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plat/arm/board/corstone700/common/corstone700_topology.c \
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plat/arm/board/corstone700/corstone700_security.c \
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plat/arm/board/corstone700/common/corstone700_security.c \
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plat/arm/board/corstone700/corstone700_plat.c \
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plat/arm/board/corstone700/common/corstone700_plat.c \
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plat/arm/board/corstone700/corstone700_pm.c \
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plat/arm/board/corstone700/common/corstone700_pm.c \
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plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \
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plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \
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${CORSTONE700_GIC_SOURCES}
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${CORSTONE700_GIC_SOURCES}
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ifneq (${ENABLE_STACK_PROTECTOR},0)
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ifneq (${ENABLE_STACK_PROTECTOR},0)
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ifneq (${ENABLE_STACK_PROTECTOR},none)
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ifneq (${ENABLE_STACK_PROTECTOR},none)
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BL32_SOURCES += plat/arm/board/corstone700/corstone700_stack_protector.c
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BL32_SOURCES += plat/arm/board/corstone700/common/corstone700_stack_protector.c
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endif
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endif
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endif
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endif
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