Commit Graph

13 Commits

Author SHA1 Message Date
Andre Przywara f2b2cc146e docs(allwinner): update SoC list and build options
Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936
2021-12-27 15:32:22 +00:00
Andre Przywara aa61699027 docs(allwinner): add SUNXI_SETUP_REGULATORS build option
Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a
2021-12-27 15:32:22 +00:00
Andre Przywara 26123ca353 allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Andre Przywara fe90f9aecf doc: allwinner: Reorder sections, document memory mapping
Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installation.

Add some ASCII art about the layout of our virtual memory map, which
uses a non-trivial condensed virtual address space.

Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Sandrine Bailleux 0396bcbc6a doc: Fix some broken links
Fix all external broken links reported by Sphinx linkcheck tool.

This does not take care of broken cross-references between internal
TF-A documentation files. These will be fixed in a future patch.

Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-07-01 13:57:20 +02:00
Mark Dykes 650a435c83 Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"
This reverts commit de9bf1d8a2.

Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f
2020-01-08 20:37:18 +00:00
Madhukar Pappireddy de9bf1d8a2 GCC: Upgrade to version 9.2-2019.12 of toolchain
This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-02 21:22:16 -06:00
Paul Beesley 29c0252959 doc: Set correct syntax highlighting style
Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.

This patch adds the correct language to each code block that doesn't
already specify it.

Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-05-22 11:28:17 +01:00
Paul Beesley 24dba2b39f doc: Reformat platform port documents
The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:

1) Make sure each port has a proper name and title (incl. owner)
2) Correct use of headings, subheadings, etc in each port
3) Resolve any naming conflicts between documents

Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-05-22 11:22:44 +01:00
Andre Przywara bed42a5d28 allwinner: Add Allwinner H6 SoC support
The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

Introduce a separate platform target, which includes a different header
file to cater for the address differences. Also add the new build target
to the documentation.

The new ATF platform name is "sun50i_h6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-03 17:06:30 +01:00
Andre Przywara 2dde1f5149 allwinner: doc: add missing paragraphs
Add two empty lines to denote the paragraphs properly and improve
readability.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-28 23:47:30 +01:00
Amit Singh Tomar dab901f83a allwinner: Add BL32 (corresponds to Trusted OS) support
This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS)
as an input using the 'SPD=<dispatcher name>' option during bl31 build.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2018-06-28 23:47:30 +01:00
Samuel Holland 64b3d9d88e allwinner: Add Allwinner A64 support
The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15 11:45:24 +01:00